# SN74GTLP1394PWR

**Texas Instruments** · Translators, Level Shifters · TSSOP-16

SN74GTLP1394PWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OEBY | input | Output enable for the Y outputs, active low (Y outputs active when low, disabled when high); LVTTL input that is 5-V tolerant. |
| 2 | Y1 | output | LVTTL feedback output carrying B1 data (true or inverted per T/C), with -24 mA/24 mA drive. |
| 3 | Y2 | output | LVTTL feedback output carrying B2 data (true or inverted per T/C), with -24 mA/24 mA drive. |
| 4 | VCC | power_in | Supply voltage, 3.15 V to 3.45 V (3.3 V nominal). |
| 5 | A1 | input | LVTTL data input for channel 1 to B1, 5-V tolerant. |
| 6 | A2 | input | LVTTL data input for channel 2 to B2, 5-V tolerant. |
| 7 | OEAB | input | Output enable for the B port, active low (B outputs active when low, disabled when high); LVTTL input that is 5-V tolerant. |
| 8 | ERC | input | Edge-rate control input selecting B-port rise/fall times: GND for slow, VCC for fast. |
| 9 | T/C | input | Polarity control: high gives true data transmission, low gives complementary (inverted) transmission in both directions. |
| 10 | VREF | power_in | B-port differential input reference voltage, 0.87 V to 1.1 V for GTLP (0.74 V to 0.87 V for GTL), normally two-thirds of VTT. |
| 11 | GND | power_in | Ground. |
| 12 | B2 | bidirectional | GTLP backplane I/O for channel 2 with 100 mA low-level drive, B-port input voltage up to VTT. |
| 13 | GND | power_in | Ground. |
| 14 | B1 | bidirectional | GTLP backplane I/O for channel 1 with 100 mA low-level drive, B-port input voltage up to VTT. |
| 15 | GND | power_in | Ground. |
| 16 | BIAS VCC | power_in | Live-insertion precharge supply for the B-port I/O, 3.15 V to 3.45 V (3.3 V nominal); precharge is disabled when any VCC pin is connected. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-16 |
| Category | Logic |
| Pins | 16 |

## CAD (KiCad official)

- Symbol: `SN74GTLP1394PWR`
- Footprint: `Package_SO:TSSOP-16_4.4x5mm_P0.65mm`
- 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files: `sn74gtlp1394pwr-etched.step` / `sn74gtlp1394pwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74gtlp1394pwr.step` / `sn74gtlp1394pwr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/sn74gtlp1394.pdf) (24 pp, sha256 `e7403dad8a68d771`, retrieved 2026-10-11, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/sn74gtlp1394pwr-datasheet.pdf)