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SN74GTL2014PWR

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Texas Instruments Translators, Level Shifters, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN74GTL2014PWR

Texas Instruments · Translators, Level Shifters · TSSOP-14

SN74GTL2014PWR from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DIR input Direction control input (LVTTL): tied to GND for GTL to LVTTL operation and to VCC for LVTTL to GTL operation.
2 B0 bidirectional GTL data input/output that operates up to 3.6 V as an open-drain port.
3 B1 bidirectional GTL data input/output that operates up to 3.6 V as an open-drain port.
4 VREF power_in GTL reference voltage input; overall recommended range is 0.5 V up to 2/3 VTT.
5 B2 bidirectional GTL data input/output that operates up to 3.6 V as an open-drain port.
6 B3 bidirectional GTL data input/output that operates up to 3.6 V as an open-drain port.
7 GND power_in Ground reference for the device.
8 GND power_in Ground reference for the device.
9 A3 bidirectional LVTTL data input/output: inputs are tolerant up to 5.5 V while outputs are not 5.5 V tolerant.
10 A2 bidirectional LVTTL data input/output: inputs are tolerant up to 5.5 V while outputs are not 5.5 V tolerant.
11 GND power_in Ground reference for the device.
12 A1 bidirectional LVTTL data input/output: inputs are tolerant up to 5.5 V while outputs are not 5.5 V tolerant.
13 A0 bidirectional LVTTL data input/output: inputs are tolerant up to 5.5 V while outputs are not 5.5 V tolerant.
14 VCC power_in Supply voltage of 3 V to 3.6 V (3.3 V nominal).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC -0.5 4.6 V 4
Input control voltages SEL VSEL -0.5 6 V SEL 4
Input voltage A port VI -0.5 7 V A port 4
Input voltage B port VI -0.5 4.6 V B port 4
Output voltage A port VO -0.5 7 V A port 4
Output voltage B port VO -0.5 4.6 V B port 4
Input clamping current IIK -50 mA VI < 0 V 4
Control input clamp current IOK -50 mA VO < 0 V 4
Current into any output in the low state IOL 40 mA A port 4
Current into any output in the low state IOL 80 mA B port 4
Current into any output in the high state IOH -40 mA 4
Storage temperature range Tstg -55 150 °C 4
Supply voltage VCC 3 3.3 3.6 V 4
Termination voltage GTL- VTT 0.85 0.9 0.95 V GTL- 4
Termination voltage GTL VTT 1.14 1.2 1.26 V GTL 4
Termination voltage GTL+ VTT 1.35 1.5 1.65 V GTL+ 4
Reference voltage overall VREF 0.5 V Overall; typ printed as 2/3 VTT, max printed as VCC/2 4
Reference voltage GTL- VREF 0.5 0.6 0.63 V GTL- 4
Reference voltage GTL VREF 0.76 0.8 0.84 V GTL 4
Reference voltage GTL+ VREF 0.87 1 1.1 V GTL+ 4
Input voltage A port VI 0 3.3 5.5 V A port; max 5.5 V (VI(max) is 3.6 V if configured as output, DIR=L) 4
Input voltage B port VI 0 3.6 V B port; nominal printed as VTT 4
High-level input voltage A port and DIR VIH 2 V A port and DIR 4
Low-level input voltage A port and DIR VIL 0.8 V A port and DIR 5
High-level input current A port IOH -20 mA A port 5
Low-level output current A port IOL 20 mA A port 5
Low-level output current B port IOL 50 mA B port 5
Low-level output voltage A port VOL 0.28 0.4 V VCC = 3 V, IOL = 8 mA 5
Low-level output voltage A port VOL 0.55 0.8 V VCC = 3 V, IOL = 16 mA 5
Low-level output voltage B port VOL 0.23 0.4 V VCC = 3 V, IOL = 40 mA 5
High-level output voltage A port VOH 2 V VCC = 3 V, IOH = -16 mA 5
Input current A port II -1 1 µA VCC = 3.6 V, VI = VCC 5
Input current A port II 5 µA VCC = 3.6 V, VI = 5.5 V 5
Input current B port II -1 1 µA VCC = 3.6 V, VI = VTT or GND 5
Input current control pin II -1 1 µA VCC = 3.6 V, VI = VCC or 0 V 5
OFF-state output current A port Ioff -10 10 µA VCC = 0 V, VIO = 0 to 3.6 V 5
OFF-state output current A port Ioff -100 100 µA VCC = 0 V, VIO 3.6 to 5.5 V 5
OFF-state output current B port Ioff -10 10 µA VCC = 0 V, VIO = 0 to 3.6 V 5
Supply current A port ICC 3 10 mA VCC = 3.6 V, VI = VCC or GND, IO = 0 5
Supply current B port ICC 3 10 mA VCC = 3.6 V, VI = VTT or GND, IO = 0 5
Additional supply current A port or control input ΔICC 500 µA VCC = 3.6 V, VI = VCC, 0.6 V 5
Input capacitance of control pin CI 2 2.5 pF VI = 3.0 V or 0 V 5
Input/output capacitance A port CIO 4 6 pF VO = 3 V or 0 5
Input/output capacitance B port CIO 5.46 5.55 pF VO = VTT or 0 5
Low to high propagation delay An to Bn tPLH 2.8 5 ns GTL-: VCC = 3.3 V ± 0.3 V, VREF = 0.6 V, VTT = 0.9 V 6
High to low propagation delay An to Bn tPHL 3.3 7 ns GTL-: VCC = 3.3 V ± 0.3 V, VREF = 0.6 V, VTT = 0.9 V 6
High to low propagation delay An to Bn tPHL 3.4 7 ns GTL: VCC = 3.3 V ± 0.3 V, VREF = 0.8 V, VTT = 1.2 V 6
Low to high propagation delay Bn to An tPLH 5.3 8 ns GTL-: VCC = 3.3 V ± 0.3 V, VREF = 0.6 V, VTT = 0.9 V 6
Low to high propagation delay Bn to An tPLH 5.2 8 ns GTL: VCC = 3.3 V ± 0.3 V, VREF = 0.8 V, VTT = 1.2 V 6
Low to high propagation delay Bn to An tPLH 5.1 8 ns GTL+: VCC = 3.3 V ± 0.3 V, VREF = 1 V, VTT = 1.5 V 6
High to low propagation delay Bn to An tPHL 5.2 8 ns GTL-: VCC = 3.3 V ± 0.3 V, VREF = 0.6 V, VTT = 0.9 V 6
High to low propagation delay Bn to An tPHL 4.9 7.16 ns GTL: VCC = 3.3 V ± 0.3 V, VREF = 0.8 V, VTT = 1.2 V 6
High to low propagation delay Bn to An tPHL 4.7 7.16 ns GTL+: VCC = 3.3 V ± 0.3 V, VREF = 1 V, VTT = 1.5 V 6
Junction-to-ambient thermal resistance RθJA 136.8 °C/W PW package, 14 pins 5
Junction-to-case (top) thermal resistance RθJC(top) 63 °C/W PW package, 14 pins 5
Junction-to-board thermal resistance RθJB 78.6 °C/W PW package, 14 pins 5

CAD (KiCad official)

  • Symbol: SN74GTL2014PWR
  • Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
  • 3D model: TSSOP-14 (KiCad packages3D, STEP)
  • 3D model files: sn74gtl2014pwr-etched.step / sn74gtl2014pwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74gtl2014pwr.step / sn74gtl2014pwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (20 pp, sha256 9ed0085fb4ab79e1, retrieved 2026-10-17, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF