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SN74F74N

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Texas Instruments Flip Flops, PDIP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN74F74N

Texas Instruments · Flip Flops · PDIP-14

SN74F74N from Texas Instruments, in a PDIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1CLR input Active-low asynchronous clear for flip-flop 1 that resets the outputs regardless of other inputs, with VIL max 0.8 V and VIH min 2 V.
2 1D input Data input of flip-flop 1, transferred to the outputs on the positive-going clock edge when PRE and CLR are high, with VIH min 2 V and VIL max 0.8 V.
3 1CLK input Positive-edge-triggered clock input of flip-flop 1, with fclock up to 80 MHz for SN74F74 and VIH min 2 V.
4 1PRE input Active-low asynchronous preset for flip-flop 1 that sets the outputs regardless of other inputs, with VIL max 0.8 V and VIH min 2 V.
5 1Q output True output of flip-flop 1, with IOH of -1 mA and IOL of 20 mA recommended maximum.
6 ~{1Q} output Complementary output of flip-flop 1, with IOH of -1 mA and IOL of 20 mA recommended maximum.
7 GND power_in Ground reference pin.
8 ~{2Q} output Complementary output of flip-flop 2, with IOH of -1 mA and IOL of 20 mA recommended maximum.
9 2Q output True output of flip-flop 2, with IOH of -1 mA and IOL of 20 mA recommended maximum.
10 2PRE input Active-low asynchronous preset for flip-flop 2 that sets the outputs regardless of other inputs, with VIL max 0.8 V and VIH min 2 V.
11 2CLK input Positive-edge-triggered clock input of flip-flop 2, with fclock up to 80 MHz for SN74F74 and VIH min 2 V.
12 2D input Data input of flip-flop 2, transferred to the outputs on the positive-going clock edge when PRE and CLR are high, with VIH min 2 V and VIL max 0.8 V.
13 2CLR input Active-low asynchronous clear for flip-flop 2 that resets the outputs regardless of other inputs, with VIL max 0.8 V and VIH min 2 V.
14 VCC power_in Supply voltage pin, recommended 4.5 V to 5.5 V with absolute maximum of 7 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package PDIP-14
Category Logic ICs
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 4.5 5 5.5 V 3
High-level input voltage VIH 2 V 3
Low-level input voltage VIL 0.8 V 3
Input clamp current IIK -18 mA 3
High-level output current IOH -1 mA 3
Low-level output current IOL 20 mA 3
Operating free-air temperature TA 0 70 °C 3
Supply voltage range VCC -0.5 7 V 2
Input voltage range VI -1.2 7 V see Note 1 2
Input current range -30 5 mA 2
Voltage applied to any output in the high state -0.5 V upper limit VCC 2
Current into any output in the low state 40 mA 2
Operating free-air temperature range 0 70 °C SN74F74 2
Storage temperature range -65 150 °C 2
Input clamp voltage VIK -1.2 V VCC = 4.5 V, II = -18 mA 3
High-level output voltage VOH 2.5 3.4 V VCC = 4.5 V, IOH =, 1 mA 3
Low-level output voltage VOL 0.3 0.5 V VCC = 4.5 V, IOL = 20 mA 3
Input current at max input voltage II 0.1 mA VCC = 5.5 V, VI = 7 V 3
High-level input current IIH 20 µA VCC = 5.5 V, VI = 2.7 V 3
Low-level input current, Data, CLK IIL -0.6 mA VCC = 5.5 V, VI = 0.5 V 3
Low-level input current, PRE or CLR IIL -1.8 mA VCC = 5.5 V, VI = 0.5 V 3
Short-circuit output current IOS -60 -150 mA VCC = 5.5 V, VO = 0 3
Supply current ICC 10.5 16 mA VCC = 5.5 V, See Note 2 3
Clock frequency fclock 0 100 MHz 3
Pulse duration, CLK high, PRE or CLR low tw 4 ns 3
Pulse duration, CLK low tw 5 ns 3
Setup time, data before CLK↑, High tsu 2 ns 3
Setup time, data before CLK↑, Low tsu 3 ns 3
Setup time, inactive-state before CLK↑ (PRE or CLR to CLK) tsu 2 ns 3
Hold time, data after CLK↑, High th 1 ns 3
Hold time, data after CLK↑, Low th 1 ns 3
Maximum clock frequency fmax 100 MHz VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX 4
Propagation delay CLK to Q or Q̄ (low-to-high) tPLH 3 7.8 ns VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX 4
Propagation delay CLK to Q or Q̄ (high-to-low) tPHL 3.6 9.2 ns VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX 4
Propagation delay PRE or CLR to Q or Q̄ (low-to-high) tPLH 2.4 7.1 ns VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX 4
Propagation delay PRE or CLR to Q or Q̄ (high-to-low) tPHL 2.7 10.5 ns VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX 4

CAD (KiCad official)

  • Symbol: SN74F74N
  • Footprint: Package_DIP:DIP-14_W7.62mm
  • 3D model: PDIP-14 (KiCad packages3D, STEP)
  • 3D model files: sn74f74n-etched.step / sn74f74n-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74f74n.step / sn74f74n.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (19 pp, sha256 8115fba14f1460fc, retrieved 2026-10-26, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF