component
SN74F74DR
Public Made by Adomby adom
Texas Instruments Flip Flops, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads on click. Unloads only if this page sits in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads on click. Unloads only if this page sits in the background.
PCB Footprint
Open full view ↗Loads on click. Unloads only if this page sits in the background.
Datasheet
Open in new tab ↗Loads on click. Unloads only if this page sits in the background.
README
markdownSN74F74DR
Texas Instruments · Flip Flops · SOIC-14
SN74F74DR from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1CLR | input | Active-low asynchronous clear for flip-flop 1 that resets 1Q low regardless of other inputs; low-level input is 0.8 V max. |
| 2 | 1D | input | Data input for flip-flop 1, transferred to the outputs on the positive-going clock edge; high-level input is 2 V min. |
| 3 | 1CLK | input | Positive-edge-triggered clock input for flip-flop 1, with maximum clock frequency of 80 MHz min to 100 MHz for SN74F74. |
| 4 | 1PRE | input | Active-low asynchronous preset for flip-flop 1 that sets 1Q high regardless of other inputs; low-level input is 0.8 V max. |
| 5 | 1Q | output | True output of flip-flop 1, rated for IOH of -1 mA and IOL of 20 mA. |
| 6 | 1Q̅ | output | Complementary output of flip-flop 1, rated for IOH of -1 mA and IOL of 20 mA. |
| 7 | GND | power_in | Ground reference pin for the device. |
| 8 | 2Q̅ | output | Complementary output of flip-flop 2, rated for IOH of -1 mA and IOL of 20 mA. |
| 9 | 2Q | output | True output of flip-flop 2, rated for IOH of -1 mA and IOL of 20 mA. |
| 10 | 2PRE | input | Active-low asynchronous preset for flip-flop 2 that sets 2Q high regardless of other inputs; low-level input is 0.8 V max. |
| 11 | 2CLK | input | Positive-edge-triggered clock input for flip-flop 2, with maximum clock frequency of 80 MHz min to 100 MHz for SN74F74. |
| 12 | 2D | input | Data input for flip-flop 2, transferred to the outputs on the positive-going clock edge; high-level input is 2 V min. |
| 13 | 2CLR | input | Active-low asynchronous clear for flip-flop 2 that resets 2Q low regardless of other inputs; low-level input is 0.8 V max. |
| 14 | VCC | power_in | Supply voltage pin, recommended 4.5 V to 5.5 V with absolute maximum of 7 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-14 |
| Category | Logic |
| Pins | 14 |
CAD (KiCad official)
- Symbol:
SN74F74DR - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files:
sn74f74dr-etched.step/sn74f74dr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74f74dr.step/sn74f74dr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (21 pp, sha256
2c2dbfa4db9f0818, retrieved 2026-09-30, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).