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SN74F373N

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Texas Instruments Latches, PDIP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN74F373N

Texas Instruments · Latches · PDIP-20

SN74F373N from Texas Instruments, in a PDIP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE input Output enable, active low: low enables the eight 3-state outputs, high places them in the high-impedance state without affecting the latches.
2 1Q tri_state 3-state latch output 1, rated for IOL 24 mA and IOH -3 mA on the SN74F373.
3 1D input Data input for latch 1, which is transparent while LE is high and latched when LE goes low.
4 2D input Data input for latch 2, which is transparent while LE is high and latched when LE goes low.
5 2Q tri_state 3-state latch output 2, rated for IOL 24 mA and IOH -3 mA on the SN74F373.
6 3Q tri_state 3-state latch output 3, rated for IOL 24 mA and IOH -3 mA on the SN74F373.
7 3D input Data input for latch 3, which is transparent while LE is high and latched when LE goes low.
8 4D input Data input for latch 4, which is transparent while LE is high and latched when LE goes low.
9 4Q tri_state 3-state latch output 4, rated for IOL 24 mA and IOH -3 mA on the SN74F373.
10 GND power_in Ground pin.
11 LE input Latch enable: outputs follow the D inputs while high, and the data is latched when LE is taken low.
12 5Q tri_state 3-state latch output 5, rated for IOL 24 mA and IOH -3 mA on the SN74F373.
13 5D input Data input for latch 5, which is transparent while LE is high and latched when LE goes low.
14 6D input Data input for latch 6, which is transparent while LE is high and latched when LE goes low.
15 6Q tri_state 3-state latch output 6, rated for IOL 24 mA and IOH -3 mA on the SN74F373.
16 7Q tri_state 3-state latch output 7, rated for IOL 24 mA and IOH -3 mA on the SN74F373.
17 7D input Data input for latch 7, which is transparent while LE is high and latched when LE goes low.
18 8D input Data input for latch 8, which is transparent while LE is high and latched when LE goes low.
19 8Q tri_state 3-state latch output 8, rated for IOL 24 mA and IOH -3 mA on the SN74F373.
20 VCC power_in Supply voltage, recommended 4.5 V to 5.5 V (absolute maximum -0.5 V to 7 V).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package PDIP-20
Category Logic ICs
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 4.5 5 5.5 V 2
High-level input voltage VIH 2 V 2
Low-level input voltage VIL 0.8 V 2
Input clamp current IIK -18 mA 2
High-level output current IOH -3 mA 2
Low-level output current IOL 24 mA 2
Operating free-air temperature TA 0 70 °C 2
Supply voltage range VCC -0.5 7 V 2
Input voltage range VI -1.2 7 V see Note 1 2
Input current range -30 5 mA 2
Voltage applied to any output in disabled or power-off state -0.5 5.5 V 2
Current into any output in the low state 48 mA SN74F373 2
Operating free-air temperature range 0 70 °C SN74F373 2
Storage temperature range -65 150 °C 2
Input clamp voltage VIK -1.2 V VCC = 4.5 V, II = -18 mA 3
High-level output voltage VOH 2.5 3.4 V VCC = 4.5 V, IOH = -1 mA 3
High-level output voltage VOH 2.4 3.3 V VCC = 4.5 V, IOH = -3 mA 3
High-level output voltage VOH 2.7 V VCC = 4.75 V, IOH = -1 mA to -3 mA 3
Low-level output voltage VOL 0.35 0.5 V VCC = 4.5 V, IOL = 24 mA 3
Off-state output current, high-level voltage applied IOZH 50 µA VCC = 5.5 V, VO = 2.7 V 3
Off-state output current, low-level voltage applied IOZL -50 µA VCC = 5.5 V, VO = 0.5 V 3
Input current at maximum input voltage II 0.1 mA VCC = 5.5 V, VI = 7 V 3
High-level input current IIH 20 µA VCC = 5.5 V, VI = 2.7 V 3
Low-level input current IIL -0.6 mA VCC = 5.5 V, VI = 0.5 V 3
Short-circuit output current IOS -60 -150 mA VCC = 5.5 V, VO = 0 3
Supply current (outputs Z) ICCZ 38 55 mA VCC = 5.5 V, See Note 2 3
Pulse duration, LE high tw 6 ns 3
Setup time, data before LE↓ tsu 2 ns 3
Hold time, data after LE↓ th 3 ns 3
Propagation delay D to Q (low-to-high) tPLH 2.2 8 ns VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX 3
Propagation delay D to Q (high-to-low) tPHL 1.2 6 ns VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX 3
Propagation delay LE to Q (low-to-high) tPLH 4.2 13 ns VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX 3
Propagation delay LE to Q (high-to-low) tPHL 2.2 8 ns VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX 3
Output enable time OE to Q (Z-to-high) tPZH 1.2 12 ns VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX 3
Output enable time OE to Q (Z-to-low) tPZL 1.2 8.5 ns VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX 3
Output disable time OE to Q (high-to-Z) tPHZ 1.2 7.5 ns VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX 3
Output disable time OE to Q (low-to-Z) tPLZ 1.2 6 ns VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX 3

CAD (KiCad official)

  • Symbol: SN74F373N
  • Footprint: Package_DIP:DIP-20_W7.62mm
  • 3D model: PDIP-20 (KiCad packages3D, STEP)
  • 3D model files: sn74f373n-etched.step / sn74f373n-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74f373n.step / sn74f373n.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (20 pp, sha256 9596fa601f1ac510, retrieved 2026-10-26, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF