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SN74F373DWR

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Texas Instruments Latches, SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN74F373DWR

Texas Instruments · Latches · SOIC-20-300mil

SN74F373DWR from Texas Instruments, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE input Active-low buffered output enable; when high, the eight 3-state outputs go to high impedance without affecting the latch contents.
2 1Q tri_state Latch 1 3-state true output; follows D while LE is high and holds the latched level when LE goes low.
3 1D input Latch 1 data input; sampled when LE falls, with setup time 2 ns and hold time 3 ns.
4 2D input Latch 2 data input; sampled when LE falls, with setup time 2 ns and hold time 3 ns.
5 2Q tri_state Latch 2 3-state true output; follows D while LE is high and holds the latched level when LE goes low.
6 3Q tri_state Latch 3 3-state true output; follows D while LE is high and holds the latched level when LE goes low.
7 3D input Latch 3 data input; sampled when LE falls, with setup time 2 ns and hold time 3 ns.
8 4D input Latch 4 data input; sampled when LE falls, with setup time 2 ns and hold time 3 ns.
9 4Q tri_state Latch 4 3-state true output; follows D while LE is high and holds the latched level when LE goes low.
10 GND power_in Ground reference for the device.
11 LE input Latch enable; while high the latches are transparent, and when taken low the outputs latch the D levels; minimum high pulse width is 6 ns.
12 5Q tri_state Latch 5 3-state true output; follows D while LE is high and holds the latched level when LE goes low.
13 5D input Latch 5 data input; sampled when LE falls, with setup time 2 ns and hold time 3 ns.
14 6D input Latch 6 data input; sampled when LE falls, with setup time 2 ns and hold time 3 ns.
15 6Q tri_state Latch 6 3-state true output; follows D while LE is high and holds the latched level when LE goes low.
16 7Q tri_state Latch 7 3-state true output; follows D while LE is high and holds the latched level when LE goes low.
17 7D input Latch 7 data input; sampled when LE falls, with setup time 2 ns and hold time 3 ns.
18 8D input Latch 8 data input; sampled when LE falls, with setup time 2 ns and hold time 3 ns.
19 8Q tri_state Latch 8 3-state true output; follows D while LE is high and holds the latched level when LE goes low.
20 VCC power_in Supply voltage; recommended 4.5 V to 5.5 V (5 V nominal) for SN74F373.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-20-300mil
Category Logic
Pins 20

CAD (KiCad official)

  • Symbol: SN74F373DWR
  • Footprint: Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm
  • 3D model: SOIC-20-300mil (KiCad packages3D, STEP)
  • 3D model files: sn74f373dwr-etched.step / sn74f373dwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74f373dwr.step / sn74f373dwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (21 pp, sha256 06a10642260340d0, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF