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SN74F126N
Public Made by Adomby adom
Texas Instruments Buffers, Drivers, Receivers, Transceivers, PDIP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSN74F126N
Texas Instruments · Buffers, Drivers, Receivers, Transceivers · PDIP-14
SN74F126N from Texas Instruments, in a PDIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1OE | input | Active-low output enable for buffer 1; when low, output 1Y is disabled to the high-impedance state. |
| 2 | 1A | input | Data input of buffer 1, with VIH minimum 2 V and VIL maximum 0.8 V; unused inputs must be held at VCC or GND. |
| 3 | 1Y | tri_state | 3-state output of buffer 1, which is high-impedance whenever 1OE is low (IOH maximum -15 mA, IOL maximum 64 mA). |
| 4 | 2OE | input | Active-low output enable for buffer 2; when low, output 2Y is disabled to the high-impedance state. |
| 5 | 2A | input | Data input of buffer 2, with VIH minimum 2 V and VIL maximum 0.8 V; unused inputs must be held at VCC or GND. |
| 6 | 2Y | tri_state | 3-state output of buffer 2, which is high-impedance whenever 2OE is low (IOH maximum -15 mA, IOL maximum 64 mA). |
| 7 | GND | power_in | Ground reference for the device. |
| 8 | 3Y | tri_state | 3-state output of buffer 3, which is high-impedance whenever 3OE is low (IOH maximum -15 mA, IOL maximum 64 mA). |
| 9 | 3A | input | Data input of buffer 3, with VIH minimum 2 V and VIL maximum 0.8 V; unused inputs must be held at VCC or GND. |
| 10 | 3OE | input | Active-low output enable for buffer 3; when low, output 3Y is disabled to the high-impedance state. |
| 11 | 4Y | tri_state | 3-state output of buffer 4, which is high-impedance whenever 4OE is low (IOH maximum -15 mA, IOL maximum 64 mA). |
| 12 | 4A | input | Data input of buffer 4, with VIH minimum 2 V and VIL maximum 0.8 V; unused inputs must be held at VCC or GND. |
| 13 | 4OE | input | Active-low output enable for buffer 4; when low, output 4Y is disabled to the high-impedance state. |
| 14 | VCC | power_in | Supply voltage, 4.5 V minimum to 5.5 V maximum (5 V nominal) per the recommended operating conditions. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | PDIP-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | -0.5 | 7 | V | 2 | ||
| Input voltage range | VI | -1.2 | 7 | V | see Note 1 | 2 | |
| Input current range | -30 | 5 | mA | 2 | |||
| Voltage applied to any output in the disabled or power-off state | -0.5 | 5.5 | V | 2 | |||
| Voltage applied to any output in the high state | -0.5 | V | upper limit printed as VCC | 2 | |||
| Current into any output in the low state | 128 | mA | 2 | ||||
| Storage temperature range | Tstg | -65 | 150 | °C | 2 | ||
| Package thermal impedance, N package | θJA | 80 | °C/W | N package; see Note 2 | 2 | ||
| Supply voltage | VCC | 4.5 | 5 | 5.5 | V | 2 | |
| High-level input voltage | VIH | 2 | V | 2 | |||
| Low-level input voltage | VIL | 0.8 | V | 2 | |||
| Input clamp current | IIK | -18 | mA | 2 | |||
| High-level output current | IOH | -15 | mA | 2 | |||
| Low-level output current | IOL | 64 | mA | 2 | |||
| Operating free-air temperature | TA | 0 | 70 | °C | 2 | ||
| Input clamp voltage | VIK | -1.2 | V | II = -18 mA; VCC = 4.5 V | 3 | ||
| High-level output voltage | VOH | 2.4 | 3.3 | V | IOH = -3 mA; VCC = 4.5 V | 3 | |
| High-level output voltage | VOH | 2 | 3.1 | V | IOH = -15 mA; VCC = 4.5 V | 3 | |
| High-level output voltage | VOH | 2.7 | V | IOH = -3 mA; VCC = 4.75 V | 3 | ||
| Low-level output voltage | VOL | 0.4 | 0.55 | V | IOL = 64 mA; VCC = 4.5 V | 3 | |
| Input current at maximum input voltage | II | 0.1 | mA | VI = 7 V; VCC = 0 | 3 | ||
| High-level input current | IIH | 20 | µA | VI = 2.7 V; VCC = 5.5 V | 3 | ||
| Low-level input current | IIL | -20 | µA | VI = 0.5 V; VCC = 5.5 V | 3 | ||
| Off-state output current, high-level voltage applied | IOZH | 50 | µA | VO = 2.7 V; VCC = 5.5 V | 3 | ||
| Off-state output current, low-level voltage applied | IOZL | -50 | µA | VO = 0.5 V; VCC = 5.5 V | 3 | ||
| Short-circuit output current | IOS | -100 | -225 | mA | VO = 0; VCC = 5.5 V | 3 | |
| Supply current, outputs high | ICCH | 20 | 30 | mA | Outputs open; VCC = 5.5 V | 3 | |
| Supply current, outputs low | ICCL | 32 | 48 | mA | Outputs open; VCC = 5.5 V | 3 | |
| Supply current, outputs disabled | ICCZ | 26 | 39 | mA | Outputs open; VCC = 5.5 V | 3 | |
| Propagation delay tPLH (A to Y) | tPLH | 2 | 4 | 6.5 | ns | From A to Y; VCC = 5 V, CL = 50 pF, RL = 500 Ω, TA = 25°C | 3 |
| Propagation delay tPLH (A to Y) | tPLH | 2 | 7 | ns | From A to Y; VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX | 3 | |
| Propagation delay tPHL (A to Y) | tPHL | 3 | 5.5 | 8 | ns | From A to Y; VCC = 5 V, CL = 50 pF, RL = 500 Ω, TA = 25°C | 3 |
| Propagation delay tPHL (A to Y) | tPHL | 2.8 | 8.5 | ns | From A to Y; VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX | 3 | |
| Enable time tPZH (OE to Y) | tPZH | 3.8 | 6 | 7.5 | ns | From OE to Y; VCC = 5 V, CL = 50 pF, RL = 500 Ω, TA = 25°C | 3 |
| Enable time tPZH (OE to Y) | tPZH | 3.3 | 8.5 | ns | From OE to Y; VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX | 3 | |
| Enable time tPZL (OE to Y) | tPZL | 3.8 | 6 | 8 | ns | From OE to Y; VCC = 5 V, CL = 50 pF, RL = 500 Ω, TA = 25°C | 3 |
| Enable time tPZL (OE to Y) | tPZL | 3.5 | 8.5 | ns | From OE to Y; VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX | 3 | |
| Disable time tPHZ (OE to Y) | tPHZ | 2 | 4.5 | 6.5 | ns | From OE to Y; VCC = 5 V, CL = 50 pF, RL = 500 Ω, TA = 25°C | 3 |
| Disable time tPHZ (OE to Y) | tPHZ | 2 | 7.5 | ns | From OE to Y; VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX | 3 | |
| Disable time tPLZ (OE to Y) | tPLZ | 3 | 5.5 | 7.5 | ns | From OE to Y; VCC = 5 V, CL = 50 pF, RL = 500 Ω, TA = 25°C | 3 |
| Disable time tPLZ (OE to Y) | tPLZ | 3 | 8 | ns | From OE to Y; VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX | 3 |
CAD (KiCad official)
- Symbol:
SN74F126N - Footprint:
Package_DIP:DIP-14_W7.62mm - 3D model: PDIP-14 (KiCad packages3D, STEP)
- 3D model files:
sn74f126n-etched.step/sn74f126n-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74f126n.step/sn74f126n.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (13 pp, sha256
0aa2d54573aff700, retrieved 2026-10-16, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).