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SN74F112DR

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by adom

Texas Instruments Flip Flops, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

markdown

SN74F112DR

Texas Instruments · Flip Flops · SOIC-16

SN74F112DR from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1CLK input Negative-edge-triggered clock input for flip-flop 1; data transfer occurs when CLK makes negative-going transition.
2 1K input K input for flip-flop 1; setup time = 3-5 ns before CLK↓, hold time = 0 ns; combined with J controls Q output.
3 1J input J input for flip-flop 1; setup time = 3-5 ns before CLK↓, hold time = 0 ns; combined with K controls Q output.
4 1PRE input Preset input for flip-flop 1 (active low); forces Q = H and Q̄ = L when PRE = L, regardless of clock or other inputs.
5 1Q output Q output for flip-flop 1; VOH = 2.5-3.4 V (at IOH = -1 mA), VOL = 0.3-0.5 V (at IOL = 20 mA).
6 1Q̄ output Inverted Q output for flip-flop 1; VOH = 2.5-3.4 V (at IOH = -1 mA), VOL = 0.3-0.5 V (at IOL = 20 mA); complements 1Q.
7 2Q̄ output Inverted Q output for flip-flop 2; VOH = 2.5-3.4 V (at IOH = -1 mA), VOL = 0.3-0.5 V (at IOL = 20 mA); complements 2Q.
8 GND power_in Ground; 0 V reference for all logic signals and circuits.
9 2Q output Q output for flip-flop 2; VOH = 2.5-3.4 V (at IOH = -1 mA), VOL = 0.3-0.5 V (at IOL = 20 mA).
10 2PRE input Preset input for flip-flop 2 (active low); forces Q = H and Q̄ = L when PRE = L, regardless of clock or other inputs.
11 2J input J input for flip-flop 2; setup time = 3-5 ns before CLK↓, hold time = 0 ns; combined with K controls Q output.
12 2K input K input for flip-flop 2; setup time = 3-5 ns before CLK↓, hold time = 0 ns; combined with J controls Q output.
13 2CLK input Negative-edge-triggered clock input for flip-flop 2; data transfer occurs when CLK makes negative-going transition.
14 2CLR input Clear input for flip-flop 2 (active low); forces Q = L and Q̄ = H when CLR = L, regardless of clock or other inputs.
15 1CLR input Clear input for flip-flop 1 (active low); forces Q = L and Q̄ = H when CLR = L, regardless of clock or other inputs.
16 VCC power_in Supply voltage; operating range = 4.5-5.5 V (recommended = 5 V); typical supply current = 12-19 mA.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16
Category Logic
Pins 16

CAD (KiCad official)

  • Symbol: SN74F112DR
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: sn74f112dr-etched.step / sn74f112dr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74f112dr.step / sn74f112dr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (15 pp, sha256 ae45534e8e63b369, retrieved 2026-10-01, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF