component
SN74F109DR
Public Made by Adomby adom
Texas Instruments Flip Flops, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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SN74F109DR
Texas Instruments · Flip Flops · SOIC-16
SN74F109DR from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1CLR | input | Active-low clear input of flip-flop 1; a low level resets the outputs regardless of the other inputs. |
| 2 | 1J | input | J data input of flip-flop 1, transferred to the outputs on the positive-going clock edge. |
| 3 | 1K | input | K data input of flip-flop 1, transferred to the outputs on the positive-going clock edge. |
| 4 | 1CLK | input | Clock input of flip-flop 1, positive-edge triggered. |
| 5 | 1PRE | input | Active-low preset input of flip-flop 1; a low level sets the outputs regardless of the other inputs. |
| 6 | 1Q | output | True output of flip-flop 1. |
| 7 | 1Q̄ | output | Complementary output of flip-flop 1. |
| 8 | GND | power_in | Ground. |
| 9 | 2Q̄ | output | Complementary output of flip-flop 2. |
| 10 | 2Q | output | True output of flip-flop 2. |
| 11 | 2PRE | input | Active-low preset input of flip-flop 2; a low level sets the outputs regardless of the other inputs. |
| 12 | 2CLK | input | Clock input of flip-flop 2, positive-edge triggered. |
| 13 | 2K | input | K data input of flip-flop 2, transferred to the outputs on the positive-going clock edge. |
| 14 | 2J | input | J data input of flip-flop 2, transferred to the outputs on the positive-going clock edge. |
| 15 | 2CLR | input | Active-low clear input of flip-flop 2; a low level resets the outputs regardless of the other inputs. |
| 16 | VCC | power_in | Supply voltage, recommended 4.5 V to 5.5 V (absolute maximum -0.5 V to 7 V). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-16 |
| Category | Logic |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
SN74F109DR - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files:
sn74f109dr-etched.step/sn74f109dr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74f109dr.step/sn74f109dr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (15 pp, sha256
1ae47aecbe483fe2, retrieved 2026-10-05, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# SN74F109DR
**Texas Instruments** · Flip Flops · SOIC-16
SN74F109DR from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1CLR | input | Active-low clear input of flip-flop 1; a low level resets the outputs regardless of the other inputs. |
| 2 | 1J | input | J data input of flip-flop 1, transferred to the outputs on the positive-going clock edge. |
| 3 | 1K | input | K data input of flip-flop 1, transferred to the outputs on the positive-going clock edge. |
| 4 | 1CLK | input | Clock input of flip-flop 1, positive-edge triggered. |
| 5 | 1PRE | input | Active-low preset input of flip-flop 1; a low level sets the outputs regardless of the other inputs. |
| 6 | 1Q | output | True output of flip-flop 1. |
| 7 | 1Q̄ | output | Complementary output of flip-flop 1. |
| 8 | GND | power_in | Ground. |
| 9 | 2Q̄ | output | Complementary output of flip-flop 2. |
| 10 | 2Q | output | True output of flip-flop 2. |
| 11 | 2PRE | input | Active-low preset input of flip-flop 2; a low level sets the outputs regardless of the other inputs. |
| 12 | 2CLK | input | Clock input of flip-flop 2, positive-edge triggered. |
| 13 | 2K | input | K data input of flip-flop 2, transferred to the outputs on the positive-going clock edge. |
| 14 | 2J | input | J data input of flip-flop 2, transferred to the outputs on the positive-going clock edge. |
| 15 | 2CLR | input | Active-low clear input of flip-flop 2; a low level resets the outputs regardless of the other inputs. |
| 16 | VCC | power_in | Supply voltage, recommended 4.5 V to 5.5 V (absolute maximum -0.5 V to 7 V). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-16 |
| Category | Logic |
| Pins | 16 |
## CAD (KiCad official)
- Symbol: `SN74F109DR`
- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`
- 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files: `sn74f109dr-etched.step` / `sn74f109dr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74f109dr.step` / `sn74f109dr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/sn74f109.pdf) (15 pp, sha256 `1ae47aecbe483fe2`, retrieved 2026-10-05, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/sn74f109dr-datasheet.pdf)