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SN74F08N

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Texas Instruments Gates, PDIP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN74F08N

Texas Instruments · Gates · PDIP-14

SN74F08N from Texas Instruments, in a PDIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Data input A of AND gate 1, with VIH min 2 V and VIL max 0.8 V and an input voltage range of -1.2 V to 7 V under absolute maximum ratings.
2 1B input Data input B of AND gate 1, with VIH min 2 V and VIL max 0.8 V and an input voltage range of -1.2 V to 7 V under absolute maximum ratings.
3 1Y output Output of AND gate 1 (Y = A • B), with recommended IOH of -1 mA and IOL of 20 mA.
4 2A input Data input A of AND gate 2, with VIH min 2 V and VIL max 0.8 V and an input voltage range of -1.2 V to 7 V under absolute maximum ratings.
5 2B input Data input B of AND gate 2, with VIH min 2 V and VIL max 0.8 V and an input voltage range of -1.2 V to 7 V under absolute maximum ratings.
6 2Y output Output of AND gate 2 (Y = A • B), with recommended IOH of -1 mA and IOL of 20 mA.
7 GND power_in Ground reference pin for the device.
8 3Y output Output of AND gate 3 (Y = A • B), with recommended IOH of -1 mA and IOL of 20 mA.
9 3A input Data input A of AND gate 3, with VIH min 2 V and VIL max 0.8 V and an input voltage range of -1.2 V to 7 V under absolute maximum ratings.
10 3B input Data input B of AND gate 3, with VIH min 2 V and VIL max 0.8 V and an input voltage range of -1.2 V to 7 V under absolute maximum ratings.
11 4Y output Output of AND gate 4 (Y = A • B), with recommended IOH of -1 mA and IOL of 20 mA.
12 4A input Data input A of AND gate 4, with VIH min 2 V and VIL max 0.8 V and an input voltage range of -1.2 V to 7 V under absolute maximum ratings.
13 4B input Data input B of AND gate 4, with VIH min 2 V and VIL max 0.8 V and an input voltage range of -1.2 V to 7 V under absolute maximum ratings.
14 VCC power_in Positive supply pin; recommended VCC is 4.5 V to 5.5 V (5 V nominal), with absolute maximum range -0.5 V to 7 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package PDIP-14
Category Logic ICs
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 4.5 5 5.5 V 2
High-level input voltage VIH 2 V 2
Low-level input voltage VIL 0.8 V 2
Input clamp current IIK -18 mA 2
High-level output current IOH -1 mA 2
Low-level output current IOL 20 mA 2
Operating free-air temperature TA 0 70 °C 2
Supply voltage range VCC -0.5 7 V 1
Input voltage range VI -1.2 7 V see Note 1 1
Input current range -30 5 mA 1
Voltage range applied to any output in the high state -0.5 V upper limit printed as VCC 1
Current into any output in the low state 40 mA 1
Operating free-air temperature range 0 70 °C 1
Storage temperature range -65 150 °C 1
Input clamp voltage VIK -1.2 V VCC = 4.5 V, II = -18 mA 2
High-level output voltage VOH 2.5 3.4 V VCC = 4.5 V, IOH =, 1 mA 2
High-level output voltage VOH 2.7 V VCC = 4.75 V, IOH =, 1 mA 2
Low-level output voltage VOL 0.3 0.5 V VCC = 4.5 V, IOL = 20 mA 2
Input current II 0.1 mA VCC = 5.5 V, VI = 7 V 2
High-level input current IIH 20 µA VCC = 5.5 V, VI = 2.7 V 2
Low-level input current IIL -0.6 mA VCC = 5.5 V, VI = 0.5 V 2
Short-circuit output current IOS -60 -150 mA VCC = 5.5 V, VO = 0 2
High-level supply current ICCH 5.5 8.3 mA VCC = 5.5 V, VI = 4.5 V 2
Low-level supply current ICCL 8.6 12.9 mA VCC = 5.5 V, VI = 0 2
Propagation delay time, low-to-high-level output (tPLH) tPLH 2.2 3.8 5.6 ns VCC = 5 V, CL = 50 pF, RL = 500 Ω, TA = 25°C; from A or B to Y 2
Propagation delay time, low-to-high-level output (tPLH) tPLH 2.2 6.6 ns VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500Ω, TA = MIN to MAX; from A or B to Y 2
Propagation delay time, high-to-low-level output (tPHL) tPHL 1.7 3.6 5.3 ns VCC = 5 V, CL = 50 pF, RL = 500 Ω, TA = 25°C; from A or B to Y 2
Propagation delay time, high-to-low-level output (tPHL) tPHL 1.7 6.3 ns VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500Ω, TA = MIN to MAX; from A or B to Y 2

CAD (KiCad official)

  • Symbol: SN74F08N
  • Footprint: Package_DIP:DIP-14_W7.62mm
  • 3D model: PDIP-14 (KiCad packages3D, STEP)
  • 3D model files: sn74f08n-etched.step / sn74f08n-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74f08n.step / sn74f08n.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (13 pp, sha256 6c342a184a7adecd, retrieved 2026-10-26, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF