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SN74F08DBR
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Texas Instruments Logic Gates, SSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+50@@ -0,0 +1,50 @@+# SN74F08DBR++**Texas Instruments** · Logic Gates · SSOP-14++SN74F08DBR from Texas Instruments, in a SSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | 1A | input | Input A to AND gate 1; logic input with VIL ≤ 0.8V (low) and VIH ≥ 2V (high) |+| 2 | 1B | input | Input B to AND gate 1; logic input with VIL ≤ 0.8V (low) and VIH ≥ 2V (high) |+| 3 | 1Y | output | Output of AND gate 1; IOH = -1 mA (sources), IOL = 20 mA (sinks) |+| 4 | 2A | input | Input A to AND gate 2; logic input with VIL ≤ 0.8V (low) and VIH ≥ 2V (high) |+| 5 | 2B | input | Input B to AND gate 2; logic input with VIL ≤ 0.8V (low) and VIH ≥ 2V (high) |+| 6 | 2Y | output | Output of AND gate 2; IOH = -1 mA (sources), IOL = 20 mA (sinks) |+| 7 | GND | power_in | Ground; power return and 0V logic reference |+| 8 | 3Y | output | Output of AND gate 3; IOH = -1 mA (sources), IOL = 20 mA (sinks) |+| 9 | 3A | input | Input A to AND gate 3; logic input with VIL ≤ 0.8V (low) and VIH ≥ 2V (high) |+| 10 | 3B | input | Input B to AND gate 3; logic input with VIL ≤ 0.8V (low) and VIH ≥ 2V (high) |+| 11 | 4Y | output | Output of AND gate 4; IOH = -1 mA (sources), IOL = 20 mA (sinks) |+| 12 | 4A | input | Input A to AND gate 4; logic input with VIL ≤ 0.8V (low) and VIH ≥ 2V (high) |+| 13 | 4B | input | Input B to AND gate 4; logic input with VIL ≤ 0.8V (low) and VIH ≥ 2V (high) |+| 14 | VCC | power_in | Positive supply voltage; VCC = 4.5V to 5.5V with 5V nominal |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SSOP-14 |+| Category | Logic |+| Pins | 14 |++## CAD (KiCad official)++- Symbol: `SN74F08DBR`+- Footprint: `Package_SO:SSOP-14_5.3x6.2mm_P0.65mm`+- 3D model: SSOP-14 (KiCad packages3D, STEP)+- 3D model files: `sn74f08dbr-etched.step` / `sn74f08dbr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74f08dbr.step` / `sn74f08dbr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/sn74f08) (16 pp, sha256 `0ea1da537c99befc`, retrieved 2026-10-07, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/sn74f08dbr-datasheet.pdf)
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logic input with VIL ≤ 0.8V (low) and VIH ≥ 2V (high)"+ },+ {+ "number": "2",+ "name": "1B",+ "type": "input",+ "description": "Input B to AND gate 1; logic input with VIL ≤ 0.8V (low) and VIH ≥ 2V (high)"+ },+ {+ "number": "3",+ "name": "1Y",+ "type": "output",+ "description": "Output of AND gate 1; IOH = -1 mA (sources), IOL = 20 mA (sinks)"+ },+ {+ "number": "4",+ "name": "2A",+ "type": "input",+ "description": "Input A to AND gate 2; logic input with VIL ≤ 0.8V (low) and VIH ≥ 2V (high)"+ },+ {+ "number": "5",+ "name": "2B",+ "type": "input",+ "description": "Input B to AND gate 2; logic input with VIL ≤ 0.8V (low) and VIH ≥ 2V (high)"+ },+ {+ "number": "6",+ "name": "2Y",+ "type": "output",+ "description": "Output of AND gate 2; IOH = -1 mA (sources), IOL = 20 mA (sinks)"+ },+ {+ "number": "7",+ "name": "GND",+ "type": "power_in",+ "description": "Ground; power return and 0V logic reference"+ },+ {+ "number": "8",+ "name": "3Y",+ "type": "output",+ "description": "Output of AND gate 3; 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