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SN74CBTLV3384PWR

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Texas Instruments Signal Switches, Multiplexers, Decoders, TSSOP-24. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN74CBTLV3384PWR

Texas Instruments · Signal Switches, Multiplexers, Decoders · TSSOP-24

SN74CBTLV3384PWR from Texas Instruments, in a TSSOP-24. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1OE input Output enable for the first 5-bit bus switch: when low, 1A1-1A5 are connected to 1B1-1B5, and when high the switch is open with a high-impedance state between the ports.
2 1B1 bidirectional B-side data port 1B1 of the first 5-bit FET bus switch, with rail-to-rail switching and Ioff support for partial-power-down operation.
3 1A1 bidirectional A-side data port 1A1 of the first 5-bit FET bus switch, with rail-to-rail switching and Ioff support for partial-power-down operation.
4 1A2 bidirectional A-side data port 1A2 of the first 5-bit FET bus switch, with rail-to-rail switching and Ioff support for partial-power-down operation.
5 1B2 bidirectional B-side data port 1B2 of the first 5-bit FET bus switch, with rail-to-rail switching and Ioff support for partial-power-down operation.
6 1B3 bidirectional B-side data port 1B3 of the first 5-bit FET bus switch, with rail-to-rail switching and Ioff support for partial-power-down operation.
7 1A3 bidirectional A-side data port 1A3 of the first 5-bit FET bus switch, with rail-to-rail switching and Ioff support for partial-power-down operation.
8 1A4 bidirectional A-side data port 1A4 of the first 5-bit FET bus switch, with rail-to-rail switching and Ioff support for partial-power-down operation.
9 1B4 bidirectional B-side data port 1B4 of the first 5-bit FET bus switch, with rail-to-rail switching and Ioff support for partial-power-down operation.
10 1B5 bidirectional B-side data port 1B5 of the first 5-bit FET bus switch, with rail-to-rail switching and Ioff support for partial-power-down operation.
11 1A5 bidirectional A-side data port 1A5 of the first 5-bit FET bus switch, with rail-to-rail switching and Ioff support for partial-power-down operation.
12 GND power_in Ground reference for the device.
13 2OE input Output enable for the second 5-bit bus switch: when low, 2A1-2A5 are connected to 2B1-2B5, and when high the switch is open with a high-impedance state between the ports.
14 2A1 bidirectional A-side data port 2A1 of the second 5-bit FET bus switch, with rail-to-rail switching and Ioff support for partial-power-down operation.
15 2B1 bidirectional B-side data port 2B1 of the second 5-bit FET bus switch, with rail-to-rail switching and Ioff support for partial-power-down operation.
16 2B2 bidirectional B-side data port 2B2 of the second 5-bit FET bus switch, with rail-to-rail switching and Ioff support for partial-power-down operation.
17 2A2 bidirectional A-side data port 2A2 of the second 5-bit FET bus switch, with rail-to-rail switching and Ioff support for partial-power-down operation.
18 2A3 bidirectional A-side data port 2A3 of the second 5-bit FET bus switch, with rail-to-rail switching and Ioff support for partial-power-down operation.
19 2B3 bidirectional B-side data port 2B3 of the second 5-bit FET bus switch, with rail-to-rail switching and Ioff support for partial-power-down operation.
20 2B4 bidirectional B-side data port 2B4 of the second 5-bit FET bus switch, with rail-to-rail switching and Ioff support for partial-power-down operation.
21 2A4 bidirectional A-side data port 2A4 of the second 5-bit FET bus switch, with rail-to-rail switching and Ioff support for partial-power-down operation.
22 2A5 bidirectional A-side data port 2A5 of the second 5-bit FET bus switch, with rail-to-rail switching and Ioff support for partial-power-down operation.
23 2B5 bidirectional B-side data port 2B5 of the second 5-bit FET bus switch, with rail-to-rail switching and Ioff support for partial-power-down operation.
24 VCC power_in Supply voltage, recommended operating range 2.3 V to 3.6 V; OE should be tied to VCC through a pullup resistor to keep the high-impedance state during power up or power down.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-24
Category Logic
Pins 24

CAD (KiCad official)

  • Symbol: SN74CBTLV3384PWR
  • Footprint: Package_SO:TSSOP-24_4.4x7.8mm_P0.65mm
  • 3D model: TSSOP-24 (KiCad packages3D, STEP)
  • 3D model files: sn74cbtlv3384pwr-etched.step / sn74cbtlv3384pwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74cbtlv3384pwr.step / sn74cbtlv3384pwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (18 pp, sha256 e14f56d5d2e8de73, retrieved 2026-10-11, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF