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README

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SN74CBT3257CPWR

Texas Instruments · Signal Switches, Multiplexers, Decoders · TSSOP-16

SN74CBT3257CPWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S input Select input that chooses the data path for the 1-of-2 multiplexer: low connects A to B1 and high connects A to B2, with control inputs TTL/5-V CMOS compatible (VIH min 2 V, VIL max 0.8 V).
2 1B1 bidirectional Switch port 1B1 of the 1A channel, connected to 1A when OE is low and S is low; data I/O supports 0 to 5.5 V and the port is protected for undershoot to −2 V.
3 1B2 bidirectional Switch port 1B2 of the 1A channel, connected to 1A when OE is low and S is high; data I/O supports 0 to 5.5 V and the port is protected for undershoot to −2 V.
4 1A bidirectional Common A port of the first 1-of-2 switch, which is connected to 1B1 or 1B2 under control of S and OE and has typical ron of 3 Ω; undershoot protected to −2 V.
5 2B1 bidirectional Switch port 2B1 of the 2A channel, connected to 2A when OE is low and S is low; data I/O supports 0 to 5.5 V and the port is protected for undershoot to −2 V.
6 2B2 bidirectional Switch port 2B2 of the 2A channel, connected to 2A when OE is low and S is high; data I/O supports 0 to 5.5 V and the port is protected for undershoot to −2 V.
7 2A bidirectional Common A port of the second 1-of-2 switch, which is connected to 2B1 or 2B2 under control of S and OE and has typical ron of 3 Ω; undershoot protected to −2 V.
8 GND power_in Device ground reference; continuous current through the GND terminal is limited to ±100 mA absolute maximum.
9 3A bidirectional Common A port of the third 1-of-2 switch, which is connected to 3B1 or 3B2 under control of S and OE and has typical ron of 3 Ω; undershoot protected to −2 V.
10 3B2 bidirectional Switch port 3B2 of the 3A channel, connected to 3A when OE is low and S is high; data I/O supports 0 to 5.5 V and the port is protected for undershoot to −2 V.
11 3B1 bidirectional Switch port 3B1 of the 3A channel, connected to 3A when OE is low and S is low; data I/O supports 0 to 5.5 V and the port is protected for undershoot to −2 V.
12 4A bidirectional Common A port of the fourth 1-of-2 switch, which is connected to 4B1 or 4B2 under control of S and OE and has typical ron of 3 Ω; undershoot protected to −2 V.
13 4B2 bidirectional Switch port 4B2 of the 4A channel, connected to 4A when OE is low and S is high; data I/O supports 0 to 5.5 V and the port is protected for undershoot to −2 V.
14 4B1 bidirectional Switch port 4B1 of the 4A channel, connected to 4A when OE is low and S is low; data I/O supports 0 to 5.5 V and the port is protected for undershoot to −2 V.
15 OE input Active-low output enable: low enables the switch path, high disables it into high-impedance between A and B; tie to VCC through a pullup during power up or down (control VIH min 2 V, VIL max 0.8 V).
16 VCC power_in Supply voltage, recommended operating range 4 V to 5.5 V, with ICC of 3 µA max at VCC = 5.5 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage range VCC -0.5 7 V 4
Control input voltage range VIN -0.5 7 V See Notes 1 and 2 4
Switch I/O voltage range VI/O -0.5 7 V See Notes 1, 2, and 3 4
Control input clamp current IIK -50 mA VIN < 0 4
I/O port clamp current II/OK -50 mA VI/O < 0 4
ON-state switch current II/O -128 128 mA See Note 4 4
Continuous current through VCC or GND terminals -100 100 mA 4
Storage temperature range Tstg -65 150 °C 4
Package thermal impedance PW package θJA 108 °C/W PW package; see Note 5 (JESD 51-7) 4
Supply voltage VCC 4 5.5 V 4
High-level control input voltage VIH 2 5.5 V 4
Low-level control input voltage VIL 0 0.8 V 4
Data input/output voltage VI/O 0 5.5 V 4
Operating free-air temperature TA -40 85 °C 4
Control inputs clamp voltage VIK -1.8 V Control inputs; VCC = 4.5 V, IIN = −18 mA 5
Data inputs clamp voltage VIKU -2 V Data inputs; VCC = 5 V, 0 mA > II ≥ −50 mA, VIN = VCC or GND, Switch OFF 5
Control inputs input leakage current IIN -1 1 µA Control inputs; VCC = 5.5 V, VIN = VCC or GND 5
Off-state I/O leakage current IOZ -10 10 µA VCC = 5.5 V, VO = 0 to 5.5 V, VI = 0, Switch OFF, VIN = VCC or GND 5
Partial power-down leakage current Ioff 10 µA VCC = 0, VO = 0 to 5.5 V, VI = 0 5
Quiescent supply current ICC 3 µA VCC = 5.5 V, II/O = 0, VIN = VCC or GND, Switch ON or OFF 5
Increase in supply current per control input ΔICC 2.5 mA Control inputs; VCC = 5.5 V, one input at 3.4 V, other inputs at VCC or GND 5
ON-state resistance at VCC = 4 V, VI = 2.4 V ron 8 12 Ω VCC = 4 V, VI = 2.4 V, IO = −15 mA 5
ON-state resistance at VCC = 4 V, VI = 0 ron 3 6 Ω VCC = 4 V, VI = 0, IO = 64 mA 5
ON-state resistance at VCC = 4.5 V, VI = 0 ron 3 6 Ω VCC = 4.5 V, VI = 0, IO = 30 mA 5
ON-state resistance at VCC = 4.5 V, VI = 2.4 V ron 5 10 Ω VCC = 4.5 V, VI = 2.4 V, IO = −15 mA 5
Propagation delay S to A (VCC = 4 V ±0.5 V) tpd(s) 6 ns S to A; CL = 50 pF; see Figure 3 5
Propagation delay S to A (VCC = 5 V ±0.5 V) tpd(s) 1.5 5.6 ns S to A; CL = 50 pF; see Figure 3 5
Enable time S to B (VCC = 4 V ±0.5 V) ten 6.3 ns S to B; CL = 50 pF; see Figure 3 5
Enable time S to B (VCC = 5 V ±0.5 V) ten 1.5 5.8 ns S to B; CL = 50 pF; see Figure 3 5
Enable time OE to A or B (VCC = 4 V ±0.5 V) ten 6.3 ns OE to A or B; CL = 50 pF; see Figure 3 5
Enable time OE to A or B (VCC = 5 V ±0.5 V) ten 1.5 5.8 ns OE to A or B; CL = 50 pF; see Figure 3 5
Disable time S to B (VCC = 4 V ±0.5 V) tdis 6.5 ns S to B; CL = 50 pF; see Figure 3 5
Disable time S to B (VCC = 5 V ±0.5 V) tdis 1.5 6 ns S to B; CL = 50 pF; see Figure 3 5
Disable time OE to A or B (VCC = 4 V ±0.5 V) tdis 5.9 ns OE to A or B; CL = 50 pF; see Figure 3 5
Disable time OE to A or B (VCC = 5 V ±0.5 V) tdis 1.5 5.9 ns OE to A or B; CL = 50 pF; see Figure 3 5
Undershoot output voltage VOUTU 2 V VCC = 5.5 V, Switch OFF, VIN = VCC or GND 6
Control input capacitance Cin 3.5 pF VIN = 3 V or 0 5
Cio(OFF) A port Cio(OFF) 8.5 pF VI/O = 3 V or 0, Switch OFF, VIN = VCC or GND 5
Cio(OFF) B port Cio(OFF) 5.5 pF VI/O = 3 V or 0, Switch OFF, VIN = VCC or GND 5
On-state input/output capacitance Cio(ON) 16.5 pF VI/O = 3 V or 0, Switch ON, VIN = VCC or GND 5
Propagation delay A or B to B or A (calculated, VCC = 4 V ±0.5 V) tpd 0.24 ns Calculated RC time constant; CL = 50 pF 5
Propagation delay A or B to B or A (calculated, VCC = 5 V) tpd 0.15 ns Calculated RC time constant; CL = 50 pF 5

CAD (KiCad official)

  • Symbol: SN74CBT3257CPWR
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: sn74cbt3257cpwr-etched.step / sn74cbt3257cpwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74cbt3257cpwr.step / sn74cbt3257cpwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (26 pp, sha256 b08cb4ed3303b0eb, retrieved 2026-10-18, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF