SN74AUP1G32DCKR

{
  "schema_version": 1,
  "type": "component",
  "slug": "sn74aup1g32dckr",
  "title": "SN74AUP1G32DCKR",
  "brief": "UMW Logic Gates, SC-70-5. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.1.0",
  "license": "CC-BY-SA-4.0",
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  "component": {
    "mpn": "SN74AUP1G32DCKR",
    "manufacturer": "UMW",
    "package": "SC-70-5",
    "pin_count": 5,
    "category": "Logic",
    "subcategory": "Logic Gates",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603018419008917504",
    "parts": {
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      "footprint": "sn74aup1g32dckr.kicad_mod",
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      "model_3d_plain": "sn74aup1g32dckr.glb",
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      "lbr": "sn74aup1g32dckr.lbr"
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    "distributor_links": {},
    "pins": [
      {
        "number": "1",
        "name": "A",
        "type": "input",
        "description": "OR gate input A. CMOS logic input, VIH = 0.75*VCC (at 0.8 V) down to 2.0 V (at 3.0-3.6 V VCC). Input leakage ±0.1 µA typ."
      },
      {
        "number": "2",
        "name": "B",
        "type": "input",
        "description": "OR gate input B. CMOS logic input, same VIH/VIL thresholds as input A."
      },
      {
        "number": "3",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference (0 V). Return for VCC supply current and logic-low output current."
      },
      {
        "number": "4",
        "name": "Y",
        "type": "output",
        "description": "OR gate output, Y = A OR B. Balanced push-pull CMOS output rated ±4 mA sink/source; VOH ≈ VCC-0.1 V at 20 µA load."
      },
      {
        "number": "5",
        "name": "VCC",
        "type": "power_in",
        "description": "Positive supply, 0.8 V to 3.6 V operating range (absolute max 4.6 V). Quiescent ICC ≤ 0.7 µA at 3.6 V; bypass with a local 0.1 µF ceramic to GND."
      }
    ],
    "provenance": {
      "extractor": "ds2sf",
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603018419008917504",
        "pages": 9,
        "sha256": "5bb48c257337a5f9",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 5,
        "described": 5,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "logic": {
      "family_id": "74AUP1G32",
      "logic_family": "74AUP",
      "function_code": "1G32",
      "function_class": "Gate",
      "function_name": "1-gate variant of Quad 2-Input OR Gate (32)",
      "manufacturer": "Texas Instruments",
      "is_specialty": false
    },
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        "seat": "z = 0",
        "extents_mm": [
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          2.0,
          1.1
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        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "2860de5b7b085919ff6e952148353f928798588d9f544dc69430545aff2ba908",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "sn74aup1g32dckr-etched.step",
        "role": "eda",
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        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
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        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
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        "sha256": "e2d1abaa922614b3261f9937ff4027c180fe12167c3e5c5c3a06c83d22c3c4c9",
        "checked": "2026-10-21",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  },
  "metadata": {
    "specs": {
      "Manufacturer": "UMW",
      "Package": "SC-70-5",
      "Category": "Logic",
      "Pins": "5"
    }
  },
  "variants": [
    {
      "mpn": "SN74AUP1G32DCKR",
      "kind": "packaging"
    },
    {
      "mpn": "SN74AUP1G32DCKRDBVR",
      "kind": "packaging"
    }
  ],
  "sections": [
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  "discovery_triggers": [
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  "discovery_pitch": "SN74AUP1G32DCKR (UMW) component page with datasheet-verified CAD.",
  "author": {
    "name": "Ray",
    "email": "[email protected]"
  },
  "dependencies": {},
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    "docs/sn74aup1g32dckr-datasheet.pdf",
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  "visibility": {
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  },
  "updated_at": "2026-09-25T06:50:28.592Z"
}