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Contents

README

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SN74AUP1G125DRLR

Texas Instruments · Buffers, Drivers, Receivers, Transceivers · SOT-553-5

SN74AUP1G125DRLR from Texas Instruments, in a SOT-553-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE input Output enable input (active low); drives output to follow input A when low, places output in high impedance when high
2 A input Input signal to the buffer; output Y follows this signal when OE is low
3 GND power_in Ground connection
4 Y output Three-state output signal; driven to follow input A when OE is low, enters high impedance when OE is high
5 VCC power_in Positive supply voltage with recommended operating range of 0.8 V to 3.6 V

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOT-553-5
Category Logic
Pins 5

CAD (KiCad official)

  • Symbol: SN74AUP1G125DRLR
  • Footprint: Package_TO_SOT_SMD:SOT-553
  • 3D model: SOT-553-5 (KiCad packages3D, STEP)
  • 3D model files: sn74aup1g125drlr-etched.step / sn74aup1g125drlr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74aup1g125drlr.step / sn74aup1g125drlr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (56 pp, sha256 a0d166e5d974254a, retrieved 2026-09-24, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF