# SN74AUP1G08DBVR-TP

**TECH PUBLIC** · Logic Gates · SOT-23-5

SN74AUP1G08DBVR-TP from TECH PUBLIC, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A | input | Gate input A; accepts voltages up to 3.6V (recommended 0 to 3.6V), Y = A·B. |
| 2 | B | input | Gate input B; accepts voltages up to 3.6V (recommended 0 to 3.6V), Y = A·B. |
| 3 | GND | power_in | Ground, 0V reference. |
| 4 | Y | output | AND gate output Y = A·B; swings 0 to VCC, continuous output current ±20mA max. |
| 5 | VCC | power_in | Supply voltage, 0.8V to 3.6V recommended operating range (absolute max -0.5 to +4.6V). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | TECH PUBLIC |
| Package | SOT-23-5 |
| Category | Logic |
| Pins | 5 |

## CAD (KiCad official)

- Symbol: `SN74AUP1G08DBVR-TP`
- Footprint: `Package_TO_SOT_SMD:SOT-23-5`
- 3D model: SOT-23-5 (KiCad packages3D, STEP)
- 3D model files: `sn74aup1g08dbvr-tp-etched.step` / `sn74aup1g08dbvr-tp-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74aup1g08dbvr-tp.step` / `sn74aup1g08dbvr-tp.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [TECH PUBLIC datasheet](docs/sn74aup1g08dbvr-tp-datasheet.pdf) (10 pp, sha256 `ee3c7610fc5dbd16`, retrieved 2026-10-17, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/sn74aup1g08dbvr-tp-datasheet.pdf)