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SN74AUC1G80DCKR

Texas Instruments · Flip Flops · SC-70-5

SN74AUC1G80DCKR from Texas Instruments, in a SC-70-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 D input Data input whose level is transferred to Q on the positive-going clock edge, with VI range 0 to 3.6 V and unused inputs held at VCC or GND.
2 CLK input Clock input that triggers on the positive edge at a voltage level not directly related to the clock rise time, with VI range 0 to 3.6 V.
3 GND power_in Ground pin, with continuous current through VCC or GND limited to ±100 mA.
4 Q output Flip-flop output, rated for ±8 mA drive at 1.8 V (IOH -8 mA / IOL 8 mA at VCC = 1.65 V), with Ioff disabling the output when powered down.
5 VCC power_in Supply pin, operational at 0.8 V to 2.7 V and designed specifically for 1.65 V to 1.95 V operation, with absolute maximum of 3.6 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SC-70-5
Category Logic
Pins 5

CAD (KiCad official)

  • Symbol: SN74AUC1G80DCKR
  • Footprint: Package_TO_SOT_SMD:SOT-353_SC-70-5
  • 3D model: SC-70-5 (KiCad packages3D, STEP)
  • 3D model files: sn74auc1g80dckr-etched.step / sn74auc1g80dckr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74auc1g80dckr.step / sn74auc1g80dckr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (16 pp, sha256 a7604bbdcd195a3c, retrieved 2026-10-07, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF