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SN74AUC1G32DCKR

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Texas Instruments Logic Gates, SC-70-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN74AUC1G32DCKR

Texas Instruments · Logic Gates · SC-70-5

SN74AUC1G32DCKR from Texas Instruments, in a SC-70-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A input Input A of the single 2-input positive-OR gate, rated 0 V to 3.6 V input voltage with -50 mA maximum input clamp current when VI < 0.
2 B input Input B of the single 2-input positive-OR gate, rated 0 V to 3.6 V input voltage with -50 mA maximum input clamp current when VI < 0.
3 GND power_in Ground reference pin; continuous current through VCC or GND is limited to ±100 mA absolute maximum.
4 Y output OR-gate output Y with ±8-mA output drive at 1.8 V and ±20-mA absolute maximum continuous output current.
5 VCC power_in Positive supply, recommended 0.8 V to 2.7 V and designed specifically for 1.65 V to 1.95 V operation, with 3.6 V absolute maximum.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SC-70-5
Category Logic
Pins 5

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC -0.5 3.6 V 4
Input voltage VI -0.5 3.6 V 4
Voltage range applied to any output in the high-impedance or power-off state VO -0.5 3.6 V 4
Input clamp current IIK -50 mA VI < 0 4
Output clamp current IOK -50 mA VO < 0 4
Continuous output current IO -20 20 mA 4
Continuous current through VCC or GND -100 100 mA 4
Storage temperature Tstg -65 150 °C 4
Electrostatic discharge, human body model V(ESD) -2000 2000 V HBM per ANSI/ESDA/JEDEC JS-001 4
Electrostatic discharge, charged device model V(ESD) -1000 1000 V CDM per JEDEC JESD22-C101 4
Supply voltage VCC 0.8 2.7 V 4
Input voltage VI 0 3.6 V 4
Output voltage VO 0 V 4
High-level input voltage VIH 1.7 V VCC = 2.3 V to 2.7 V 4
Low-level input voltage VIL 0 V VCC = 0.8 V 4
Low-level input voltage VIL 0.7 V VCC = 2.3 V to 2.7 V 4
High-level output current IOH -0.7 mA VCC = 0.8 V 4
High-level output current IOH -3 mA VCC = 1.1 V 4
High-level output current IOH -5 mA VCC = 1.4 V 4
High-level output current IOH -8 mA VCC = 1.65 V 4
High-level output current IOH -9 mA VCC = 2.3 V 4
Low-level output current IOL 0.7 mA VCC = 0.8 V 4
Low-level output current IOL 3 mA VCC = 1.1 V 4
Low-level output current IOL 5 mA VCC = 1.4 V 4
Low-level output current IOL 8 mA VCC = 1.65 V 4
Low-level output current IOL 9 mA VCC = 2.3 V 4
Input transition rise or fall rate Δt/Δv 20 ns/V 4
Operating free-air temperature TA -40 85 °C 5
Junction-to-ambient thermal resistance RθJA 252 °C/W DCK package (SC70, 5 pins) 5
High-level output voltage VOH 0.55 V IOH = -0.7 mA; VCC = 0.8 V 5
High-level output voltage VOH 0.8 V IOH = -3 mA; VCC = 1.1 V 5
High-level output voltage VOH 1 V IOH = -5 mA; VCC = 1.4 V 5
High-level output voltage VOH 1.2 V IOH = -8 mA; VCC = 1.65 V 5
High-level output voltage VOH 1.8 V IOH = -9 mA; VCC = 2.3 V 5
Low-level output voltage VOL 0.2 V IOL = 100 µA; VCC = 0.8 V to 2.7 V 5
Low-level output voltage VOL 0.25 V IOL = 0.7 mA; VCC = 0.8 V 5
Low-level output voltage VOL 0.3 V IOL = 3 mA; VCC = 1.1 V 5
Low-level output voltage VOL 0.4 V IOL = 5 mA; VCC = 1.4 V 5
Low-level output voltage VOL 0.45 V IOL = 8 mA; VCC = 1.65 V 5
Low-level output voltage VOL 0.6 V IOL = 9 mA; VCC = 2.3 V 5
Input current, A or B input II -5 5 µA VI = VCC or GND; VCC = 0 to 2.7 V 5
Partial-power-down input/output leakage current Ioff -10 10 µA VI or VO = 2.7 V; VCC = 0 5
Supply current ICC 10 µA VI = VCC or GND, IO = 0; VCC = 0.8 V to 2.7 V 5
Propagation delay A or B to Y, CL = 15 pF tpd 1 3.5 ns VCC = 1.2 V ± 0.1 V 5
Propagation delay A or B to Y, CL = 15 pF tpd 0.6 2.3 ns VCC = 1.5 V ± 0.1 V 5
Propagation delay A or B to Y, CL = 15 pF tpd 0.5 0.9 1.5 ns VCC = 1.8 V ± 0.15 V 5
Propagation delay A or B to Y, CL = 15 pF tpd 0.3 1.4 ns VCC = 2.5 V ± 0.2 V 5
Propagation delay A or B to Y, CL = 30 pF tpd 0.8 1.4 2.4 ns VCC = 1.8 V ± 0.15 V 5
Propagation delay A or B to Y, CL = 30 pF tpd 0.6 2.1 ns VCC = 2.5 V ± 0.2 V 5

CAD (KiCad official)

  • Symbol: SN74AUC1G32DCKR
  • Footprint: Package_TO_SOT_SMD:SOT-353_SC-70-5
  • 3D model: SC-70-5 (KiCad packages3D, STEP)
  • 3D model files: sn74auc1g32dckr-etched.step / sn74auc1g32dckr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74auc1g32dckr.step / sn74auc1g32dckr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (26 pp, sha256 8a7e67cde4f42a85, retrieved 2026-10-21, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus off (skipped (clean text read)), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF