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Contents

README

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SN74AUC1G00DBVR

Texas Instruments · Logic Gates · SOT-23-5

SN74AUC1G00DBVR from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A input Input A of the 2-input NAND gate; voltage range 0 to 3.6 V per recommended operating conditions.
2 B input Input B of the 2-input NAND gate; voltage range 0 to 3.6 V per recommended operating conditions.
3 GND power_in Ground reference and negative power rail.
4 Y output Output Y of the 2-input NAND gate; voltage range 0 to VCC V per recommended operating conditions.
5 VCC power_in Positive power supply; operating voltage range 0.8 to 2.7 V per recommended operating conditions.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOT-23-5
Category Logic
Pins 5

CAD (KiCad official)

  • Symbol: SN74AUC1G00DBVR
  • Footprint: Package_TO_SOT_SMD:SOT-23-5
  • 3D model: SOT-23-5 (KiCad packages3D, STEP)
  • 3D model files: sn74auc1g00dbvr-etched.step / sn74auc1g00dbvr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74auc1g00dbvr.step / sn74auc1g00dbvr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (22 pp, sha256 41e0848cbd45981f, retrieved 2026-09-24, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF