component

SN74AS573ADW

Public Made by Adom

by adom

Texas Instruments Latches, SOIC-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogicsn74as573adwfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads on click. Unloads only if this page sits in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads on click. Unloads only if this page sits in the background.

PCB Footprint

Open full view ↗
Loads on click. Unloads only if this page sits in the background.

Datasheet

Open in new tab ↗
Loads on click. Unloads only if this page sits in the background.
Download PDF
Contents

README

markdown

SN74AS573ADW

Texas Instruments · Latches · SOIC-20

SN74AS573ADW from Texas Instruments, in a SOIC-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE input Buffered output-enable input: when low the eight outputs take their normal logic states, and when high the outputs go to the high-impedance state without affecting the latches.
2 1D input Data input to latch channel 1; while LE is high the output 1Q follows this input, and it is latched when LE goes low.
3 2D input Data input to latch channel 2; while LE is high the output 2Q follows this input, and it is latched when LE goes low.
4 3D input Data input to latch channel 3; while LE is high the output 3Q follows this input, and it is latched when LE goes low.
5 4D input Data input to latch channel 4; while LE is high the output 4Q follows this input, and it is latched when LE goes low.
6 5D input Data input to latch channel 5; while LE is high the output 5Q follows this input, and it is latched when LE goes low.
7 6D input Data input to latch channel 6; while LE is high the output 6Q follows this input, and it is latched when LE goes low.
8 7D input Data input to latch channel 7; while LE is high the output 7Q follows this input, and it is latched when LE goes low.
9 8D input Data input to latch channel 8; while LE is high the output 8Q follows this input, and it is latched when LE goes low.
10 GND power_in Ground reference for the device.
11 LE input Latch-enable input: while high the latches are transparent to D, and when low the outputs are latched; data must meet the setup and hold times around the falling edge of LE.
12 8Q tri_state Latch 8 3-state buffer output that drives bus lines directly, is high-impedance when OE is high, and is rated at IOL 48 mA and IOH −15 mA (recommended) for the AS version.
13 7Q tri_state Latch 7 3-state buffer output that drives bus lines directly, is high-impedance when OE is high, and is rated at IOL 48 mA and IOH −15 mA (recommended) for the AS version.
14 6Q tri_state Latch 6 3-state buffer output that drives bus lines directly, is high-impedance when OE is high, and is rated at IOL 48 mA and IOH −15 mA (recommended) for the AS version.
15 5Q tri_state Latch 5 3-state buffer output that drives bus lines directly, is high-impedance when OE is high, and is rated at IOL 48 mA and IOH −15 mA (recommended) for the AS version.
16 4Q tri_state Latch 4 3-state buffer output that drives bus lines directly, is high-impedance when OE is high, and is rated at IOL 48 mA and IOH −15 mA (recommended) for the AS version.
17 3Q tri_state Latch 3 3-state buffer output that drives bus lines directly, is high-impedance when OE is high, and is rated at IOL 48 mA and IOH −15 mA (recommended) for the AS version.
18 2Q tri_state Latch 2 3-state buffer output that drives bus lines directly, is high-impedance when OE is high, and is rated at IOL 48 mA and IOH −15 mA (recommended) for the AS version.
19 1Q tri_state Latch 1 3-state buffer output that drives bus lines directly, is high-impedance when OE is high, and is rated at IOL 48 mA and IOH −15 mA (recommended) for the AS version.
20 VCC power_in Supply voltage; recommended range 4.5 V to 5.5 V (nominal 5 V) for the SN74AS573A.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-20
Category Logic
Pins 20

CAD (KiCad official)

  • Symbol: SN74AS573ADW
  • Footprint: Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm
  • 3D model: SOIC-20 (KiCad packages3D, STEP)
  • 3D model files: sn74as573adw-etched.step / sn74as573adw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74as573adw.step / sn74as573adw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (24 pp, sha256 54ce4b4f857c15f9, retrieved 2026-10-07, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF