component
SN74AS30DR
Public Made by Adomby adom
Texas Instruments Logic Gates, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+50@@ -0,0 +1,50 @@+# SN74AS30DR++**Texas Instruments** · Logic Gates · SOIC-14++SN74AS30DR from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | A | input | NAND gate input A, with VIH min 2 V, VIL max 0.8 V and input voltage range of -0.5 V to 7 V. |+| 2 | B | input | NAND gate input B, with VIH min 2 V, VIL max 0.8 V and input voltage range of -0.5 V to 7 V. |+| 3 | C | input | NAND gate input C, with VIH min 2 V, VIL max 0.8 V and input voltage range of -0.5 V to 7 V. |+| 4 | D | input | NAND gate input D, with VIH min 2 V, VIL max 0.8 V and input voltage range of -0.5 V to 7 V. |+| 5 | E | input | NAND gate input E, with VIH min 2 V, VIL max 0.8 V and input voltage range of -0.5 V to 7 V. |+| 6 | F | input | NAND gate input F, with VIH min 2 V, VIL max 0.8 V and input voltage range of -0.5 V to 7 V. |+| 7 | GND | power_in | Ground reference for the device. |+| 8 | Y | output | NAND gate output, low only when all inputs A-H are high, rated for IOH of -2 mA and IOL of 20 mA for the 'AS30. |+| 9 | N.C. | unconnected | No internal connection. |+| 10 | N.C. | unconnected | No internal connection. |+| 11 | G | input | NAND gate input G, with VIH min 2 V, VIL max 0.8 V and input voltage range of -0.5 V to 7 V. |+| 12 | H | input | NAND gate input H, with VIH min 2 V, VIL max 0.8 V and input voltage range of -0.5 V to 7 V. |+| 13 | N.C. | unconnected | No internal connection. |+| 14 | VCC | power_in | Supply voltage, recommended 4.5 V to 5.5 V (nominal 5 V), absolute maximum 7 V. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-14 |+| Category | Logic |+| Pins | 14 |++## CAD (KiCad official)++- Symbol: `SN74AS30DR`+- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`+- 3D model: SOIC-14 (KiCad packages3D, STEP)+- 3D model files: `sn74as30dr-etched.step` / `sn74as30dr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74as30dr.step` / `sn74as30dr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/sn74as30.pdf) (25 pp, sha256 `3d6478e4f4ae66a6`, retrieved 2026-10-08, tier: manufacturer)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/sn74as30dr-datasheet.pdf)
page.jsonadded+236@@ -0,0 +1,236 @@+{+ "slug": "sn74as30dr",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Logic Gates, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "logic",+ "sn74as30dr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "sn74as30dr.kicad_sym",+ "sn74as30dr.kicad_mod",+ "sn74as30dr.glb",+ "sn74as30dr.step",+ "sn74as30dr.lbr",+ "docs/hero.png",+ "docs/sn74as30dr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "sn74as30dr-hero.glb",+ "sn74as30dr-hero.overlay.json"+ ],+ "component": {+ "mpn": "SN74AS30DR",+ "manufacturer": "Texas Instruments",+ "package": "SOIC-14",+ "pin_count": 14,+ "category": "Logic",+ "subcategory": "Logic Gates",+ "datasheet": "https://www.ti.com/lit/ds/symlink/sn74as30.pdf",+ "parts": {+ "symbol": "sn74as30dr.kicad_sym",+ "footprint": "sn74as30dr.kicad_mod",+ "model_3d": "sn74as30dr-hero.glb",+ "model_3d_plain": "sn74as30dr.glb",+ "model_3d_step": "sn74as30dr-etched.step",+ "model_3d_step_plain": "sn74as30dr.step",+ "lbr": "sn74as30dr.lbr"+ },+ "distributor_links": {+ "lcsc": "C2878594",+ "digikey": "296-6353-2-ND",+ "mouser": "595-SN74AS30DR"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T00:31:39Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-6353-2-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-SN74AS30DR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "A",+ "type": "input",+ "description": "NAND gate input A, with VIH min 2 V, VIL max 0.8 V and input voltage range of -0.5 V to 7 V."+ },+ {+ "number": "2",+ "name": "B",+ "type": "input",+ "description": "NAND gate input B, with VIH min 2 V, VIL max 0.8 V and input voltage range of -0.5 V to 7 V."+ },+ {+ "number": "3",+ "name": "C",+ "type": "input",+ "description": "NAND gate input C, with VIH min 2 V, VIL max 0.8 V and input voltage range of -0.5 V to 7 V."+ },+ {+ "number": "4",+ "name": "D",+ "type": "input",+ "description": "NAND gate input D, with VIH min 2 V, VIL max 0.8 V and input voltage range of -0.5 V to 7 V."+ },+ {+ "number": "5",+ "name": "E",+ "type": "input",+ "description": "NAND gate input E, with VIH min 2 V, VIL max 0.8 V and input voltage range of -0.5 V to 7 V."+ },+ {+ "number": "6",+ "name": "F",+ "type": "input",+ "description": "NAND gate input F, with VIH min 2 V, VIL max 0.8 V and input voltage range of -0.5 V to 7 V."+ },+ {+ "number": "7",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference for the device."+ },+ {+ "number": "8",+ "name": "Y",+ "type": "output",+ "description": "NAND gate output, low only when all inputs A-H are high, rated for IOH of -2 mA and IOL of 20 mA for the 'AS30."+ },+ {+ "number": "9",+ "name": "N.C.",+ "type": "unconnected",+ "description": "No internal connection."+ },+ {+ "number": "10",+ "name": "N.C.",+ "type": "unconnected",+ "description": "No internal connection."+ },+ {+ "number": "11",+ "name": "G",+ "type": "input",+ "description": "NAND gate input G, with VIH min 2 V, VIL max 0.8 V and input voltage range of -0.5 V to 7 V."+ },+ {+ "number": "12",+ "name": "H",+ "type": "input",+ "description": "NAND gate input H, with VIH min 2 V, VIL max 0.8 V and input voltage range of -0.5 V to 7 V."+ },+ {+ "number": "13",+ "name": "N.C.",+ "type": "unconnected",+ "description": "No internal connection."+ },+ {+ "number": "14",+ "name": "VCC",+ "type": "power_in",+ "description": "Supply voltage, recommended 4.5 V to 5.5 V (nominal 5 V), absolute maximum 7 V."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The datasheet's logic symbol lists pin numbers and letters in a scrambled order; the mapping H=11 an; Pins 9, 10 and 13 are not drawn in the logic symbol and the extracted top-view text for the D/DB/N p"+ ],+ "pages_sent": 25,+ "cost_usd": 0.0872,+ "at": "2026-10-08T00:31:21"+ },+ "datasheet": {+ "url": "https://www.ti.com/lit/ds/symlink/sn74as30.pdf",+ "pages": 25,+ "sha256": "3d6478e4f4ae66a6",+ "source_tier": "mfr"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 14,+ "described": 14,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "sn74as30dr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 8.7,+ 1.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "3b9a775da256c8afcc28dcddfbc2eb3f266107fe61ce8446d96f2c52b6f44a70",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "sn74as30dr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 8.7,+ 1.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "ac4306aba38071f946977350f0eb7df6c41845e9bcdae4468e4368eaa6c0d630",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}