component
SN74AS109AD
Public Made by Adomby adom
Texas Instruments Flip Flops, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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{
"number": "1",
"name": "1CLR",
"type": "input",
"description": "Active-low asynchronous clear for flip-flop 1; a low level resets 1Q low regardless of the levels of the other inputs, and it must be high for clocked J-K operation."
},
{
"number": "2",
"name": "1J",
"type": "input",
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{
"number": "3",
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},
{
"number": "4",
"name": "1CLK",
"type": "input",
"description": "Positive-edge clock input for flip-flop 1; the datasheet specifies a maximum clock frequency of 105 MHz for the SN74AS109A."
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{
"number": "5",
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"type": "input",
"description": "Active-low asynchronous preset for flip-flop 1; a low level sets 1Q high regardless of the levels of the other inputs, with a minimum low pulse duration of 4 ns."
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{
"number": "6",
"name": "1Q",
"type": "output",
"description": "True output of flip-flop 1."
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{
"number": "7",
"name": "1Q̄",
"type": "output",
"description": "Complementary (inverted) output of flip-flop 1."
},
{
"number": "8",
"name": "GND",
"type": "power_in",
"description": "Ground reference for the device."
},
{
"number": "9",
"name": "2Q̄",
"type": "output",
"description": "Complementary (inverted) output of flip-flop 2."
},
{
"number": "10",
"name": "2Q",
"type": "output",
"description": "True output of flip-flop 2."
},
{
"number": "11",
"name": "2PRE",
"type": "input",
"description": "Active-low asynchronous preset for flip-flop 2; a low level sets 2Q high regardless of the levels of the other inputs, with a minimum low pulse duration of 4 ns."
},
{
"number": "12",
"name": "2CLK",
"type": "input",
"description": "Positive-edge clock input for flip-flop 2; the datasheet specifies a maximum clock frequency of 105 MHz for the SN74AS109A."
},
{
"number": "13",
"name": "2K",
"type": "input",
"description": "K data input of flip-flop 2, transferred to the outputs on the positive-going CLK edge when PRE and CLR are inactive (high), with a recommended setup time of 5.5 ns and hold time of 0 ns before and after CLK rises."
},
{
"number": "14",
"name": "2J",
"type": "input",
"description": "J data input of flip-flop 2, transferred to the outputs on the positive-going CLK edge when PRE and CLR are inactive (high), with a recommended setup time of 5.5 ns and hold time of 0 ns before and after CLK rises."
},
{
"number": "15",
"name": "2CLR",
"type": "input",
"description": "Active-low asynchronous clear for flip-flop 2; a low level resets 2Q low regardless of the levels of the other inputs, and it must be high for clocked J-K operation."
},
{
"number": "16",
"name": "VCC",
"type": "power_in",
"description": "Supply voltage; recommended operating range 4.5 V to 5.5 V (nominal 5 V), with an absolute maximum of 7 V."
}
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