component
SN74AS1032AN
Public Made by Adomby adom
Texas Instruments Gates, PDIP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 10h ago |
| viewers | 10h ago |
| package.json | 10h ago |
| page.json | 10h ago |
| README.md | 10h ago |
| sn74as1032an-etched.glb | 10h ago |
| sn74as1032an-etched.step | 10h ago |
| sn74as1032an-hero.glb | 10h ago |
| sn74as1032an-hero.overlay.json | 10h ago |
| sn74as1032an.glb | 10h ago |
| sn74as1032an.kicad_mod | 10h ago |
| sn74as1032an.kicad_sym | 10h ago |
| sn74as1032an.lbr | 10h ago |
| sn74as1032an.step | 10h ago |
| verification.json | 10h ago |
SN74AS1032AN
Texas Instruments · Gates · PDIP-14
SN74AS1032AN from Texas Instruments, in a PDIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Data input A of gate 1 (2-input positive-OR buffer/driver); VIH minimum 2 V and VIL maximum 0.8 V. |
| 2 | 1B | input | Data input B of gate 1 (2-input positive-OR buffer/driver); VIH minimum 2 V and VIL maximum 0.8 V. |
| 3 | 1Y | output | Output of gate 1, Y = A + B; rated up to IOH −48 mA and IOL 48 mA with high capacitive-drive capability. |
| 4 | 2A | input | Data input A of gate 2 (2-input positive-OR buffer/driver); VIH minimum 2 V and VIL maximum 0.8 V. |
| 5 | 2B | input | Data input B of gate 2 (2-input positive-OR buffer/driver); VIH minimum 2 V and VIL maximum 0.8 V. |
| 6 | 2Y | output | Output of gate 2, Y = A + B; rated up to IOH −48 mA and IOL 48 mA with high capacitive-drive capability. |
| 7 | GND | power_in | Ground reference for the device. |
| 8 | 3Y | output | Output of gate 3, Y = A + B; rated up to IOH −48 mA and IOL 48 mA with high capacitive-drive capability. |
| 9 | 3A | input | Data input A of gate 3 (2-input positive-OR buffer/driver); VIH minimum 2 V and VIL maximum 0.8 V. |
| 10 | 3B | input | Data input B of gate 3 (2-input positive-OR buffer/driver); VIH minimum 2 V and VIL maximum 0.8 V. |
| 11 | 4Y | output | Output of gate 4, Y = A + B; rated up to IOH −48 mA and IOL 48 mA with high capacitive-drive capability. |
| 12 | 4A | input | Data input A of gate 4 (2-input positive-OR buffer/driver); VIH minimum 2 V and VIL maximum 0.8 V. |
| 13 | 4B | input | Data input B of gate 4 (2-input positive-OR buffer/driver); VIH minimum 2 V and VIL maximum 0.8 V. |
| 14 | VCC | power_in | Supply voltage, recommended 4.5 V to 5.5 V (5 V nominal); absolute maximum 7 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | PDIP-14 |
| Category | Logic ICs |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | 4.5 | 5 | 5.5 | V | 2 | |
| High-level input voltage | VIH | 2 | V | 2 | |||
| Low-level input voltage | VIL | 0.8 | V | 2 | |||
| High-level output current | IOH | -48 | mA | 2 | |||
| Low-level output current | IOL | 48 | mA | 2 | |||
| Operating free-air temperature | TA | 0 | 70 | °C | 2 | ||
| Supply voltage | VCC | 7 | V | 2 | |||
| Input voltage | VI | 7 | V | 2 | |||
| Storage temperature range | Tstg | -65 | 150 | °C | 2 | ||
| Input clamp voltage | VIK | -1.2 | V | VCC = 4.5 V, II = −18 mA | 2 | ||
| High-level output voltage | VOH | 2.4 | 3.2 | V | IOH = −3 mA | 2 | |
| High-level output voltage | VOH | 2 | V | VCC = 4.5 V, IOH = −48 mA | 2 | ||
| Low-level output voltage | VOL | 0.35 | 0.5 | V | VCC = 4.5 V, IOL = 48 mA | 2 | |
| Input current at maximum input voltage | II | 0.1 | mA | VCC = 5.5 V, VI = 7 V | 2 | ||
| High-level input current | IIH | 20 | µA | VCC = 5.5 V, VI = 2.7 V | 2 | ||
| Low-level input current | IIL | -0.5 | mA | VCC = 5.5 V, VI = 0.4 V | 2 | ||
| Output current | IO | -50 | -200 | mA | VCC = 5.5 V, VO = 2.25 V | 2 | |
| Supply current, outputs high | ICCH | 7.7 | 11.5 | mA | VCC = 5.5 V, VI = 4.5 V | 2 | |
| Supply current, outputs low | ICCL | 14.7 | 24 | mA | VCC = 5.5 V, VI = 0 | 2 | |
| Propagation delay time, low-to-high-level output (A or B to Y) | tPLH | 1 | 6.3 | ns | VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX | 3 | |
| Propagation delay time, high-to-low-level output (A or B to Y) | tPHL | 1 | 6.3 | ns | VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX | 3 |
CAD (KiCad official)
- Symbol:
SN74AS1032AN - Footprint:
Package_DIP:DIP-14_W7.62mm - 3D model: PDIP-14 (KiCad packages3D, STEP)
- 3D model files:
sn74as1032an-etched.step/sn74as1032an-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74as1032an.step/sn74as1032an.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (11 pp, sha256
bebc4e714728ad7e, retrieved 2026-10-31, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).