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SN74AS1032AD

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Texas Instruments Logic Gates, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN74AS1032AD

Texas Instruments · Logic Gates · SOIC-14

SN74AS1032AD from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Input A of gate 1; with 1B forms the positive-OR function 1Y = 1A + 1B, and input levels must meet VIH min 2 V and VIL max 0.8 V.
2 1B input Input B of gate 1; with 1A forms the positive-OR function 1Y = 1A + 1B, and input levels must meet VIH min 2 V and VIL max 0.8 V.
3 1Y output Output of gate 1 (Y = A + B); the datasheet rates it for IOH down to −48 mA and IOL up to 48 mA with high capacitive-drive capability.
4 2A input Input A of gate 2; with 2B forms the positive-OR function 2Y = 2A + 2B, and input levels must meet VIH min 2 V and VIL max 0.8 V.
5 2B input Input B of gate 2; with 2A forms the positive-OR function 2Y = 2A + 2B, and input levels must meet VIH min 2 V and VIL max 0.8 V.
6 2Y output Output of gate 2 (Y = A + B); the datasheet rates it for IOH down to −48 mA and IOL up to 48 mA with high capacitive-drive capability.
7 GND power_in Ground reference pin for the device.
8 3Y output Output of gate 3 (Y = A + B); the datasheet rates it for IOH down to −48 mA and IOL up to 48 mA with high capacitive-drive capability.
9 3A input Input A of gate 3; with 3B forms the positive-OR function 3Y = 3A + 3B, and input levels must meet VIH min 2 V and VIL max 0.8 V.
10 3B input Input B of gate 3; with 3A forms the positive-OR function 3Y = 3A + 3B, and input levels must meet VIH min 2 V and VIL max 0.8 V.
11 4Y output Output of gate 4 (Y = A + B); the datasheet rates it for IOH down to −48 mA and IOL up to 48 mA with high capacitive-drive capability.
12 4A input Input A of gate 4; with 4B forms the positive-OR function 4Y = 4A + 4B, and input levels must meet VIH min 2 V and VIL max 0.8 V.
13 4B input Input B of gate 4; with 4A forms the positive-OR function 4Y = 4A + 4B, and input levels must meet VIH min 2 V and VIL max 0.8 V.
14 VCC power_in Supply voltage pin; the datasheet recommends VCC of 4.5 V to 5.5 V (nominal 5 V).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 4.5 5 5.5 V 2
High-level input voltage VIH 2 V 2
Low-level input voltage VIL 0.8 V 2
High-level output current IOH -48 mA 2
Low-level output current IOL 48 mA 2
Operating free-air temperature TA 0 70 °C 2
Supply voltage VCC 7 V 2
Input voltage VI 7 V 2
Operating free-air temperature range, SN74AS1032A TA 0 70 °C 2
Storage temperature range Tstg -65 150 °C 2
Input clamp voltage VIK -1.2 V VCC = 4.5 V, II = −18 mA 2
High-level output voltage VOH 2.4 3.2 V IOH = −3 mA 2
High-level output voltage VOH 2 V VCC = 4.5 V, IOH = −48 mA 2
Low-level output voltage VOL 0.35 0.5 V VCC = 4.5 V, IOL = 48 mA 2
Input current at maximum input voltage II 0.1 mA VCC = 5.5 V, VI = 7 V 2
High-level input current IIH 20 µA VCC = 5.5 V, VI = 2.7 V 2
Low-level input current IIL -0.5 mA VCC = 5.5 V, VI = 0.4 V 2
Short-circuit output current IO -50 -200 mA VCC = 5.5 V, VO = 2.25 V 2
Supply current, outputs high ICCH 7.7 11.5 mA VCC = 5.5 V, VI = 4.5 V 2
Supply current, outputs low ICCL 14.7 24 mA VCC = 5.5 V, VI = 0 2
Propagation delay low-to-high tPLH 1 6.3 ns VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX 3
Propagation delay high-to-low tPHL 1 6.3 ns VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX 3

CAD (KiCad official)

  • Symbol: SN74AS1032AD
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOIC-14 (KiCad packages3D, STEP)
  • 3D model files: sn74as1032ad-etched.step / sn74as1032ad-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74as1032ad.step / sn74as1032ad.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (11 pp, sha256 bebc4e714728ad7e, retrieved 2026-10-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF