component
SN74AS00DR
Public Made by Adomby adom
Texas Instruments Logic Gates, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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SN74AS00DR
Texas Instruments · Logic Gates · SOIC-14
SN74AS00DR from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Input A of gate 1, a 2-input positive NAND where Y = A • B; the absolute maximum input voltage is 7 V. |
| 2 | 1B | input | Input B of gate 1, a 2-input positive NAND where Y = A • B; the absolute maximum input voltage is 7 V. |
| 3 | 1Y | output | Output of gate 1 (Y = A • B); for SN74AS00 the recommended high-level output current is −2 mA and the low-level output current is 20 mA. |
| 4 | 2A | input | Input A of gate 2, a 2-input positive NAND where Y = A • B; the absolute maximum input voltage is 7 V. |
| 5 | 2B | input | Input B of gate 2, a 2-input positive NAND where Y = A • B; the absolute maximum input voltage is 7 V. |
| 6 | 2Y | output | Output of gate 2 (Y = A • B); for SN74AS00 the recommended high-level output current is −2 mA and the low-level output current is 20 mA. |
| 7 | GND | power_in | Ground reference pin of the device. |
| 8 | 3Y | output | Output of gate 3 (Y = A • B); for SN74AS00 the recommended high-level output current is −2 mA and the low-level output current is 20 mA. |
| 9 | 3A | input | Input A of gate 3, a 2-input positive NAND where Y = A • B; the absolute maximum input voltage is 7 V. |
| 10 | 3B | input | Input B of gate 3, a 2-input positive NAND where Y = A • B; the absolute maximum input voltage is 7 V. |
| 11 | 4Y | output | Output of gate 4 (Y = A • B); for SN74AS00 the recommended high-level output current is −2 mA and the low-level output current is 20 mA. |
| 12 | 4A | input | Input A of gate 4, a 2-input positive NAND where Y = A • B; the absolute maximum input voltage is 7 V. |
| 13 | 4B | input | Input B of gate 4, a 2-input positive NAND where Y = A • B; the absolute maximum input voltage is 7 V. |
| 14 | VCC | power_in | Supply voltage pin; recommended range 4.5 V to 5.5 V (nominal 5 V) with an absolute maximum of 7 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | 4.5 | 5 | 5.5 | V | 4 | |
| High-level input voltage | VIH | 2 | V | 4 | |||
| Low-level input voltage | VIL | 0.8 | V | 4 | |||
| High-level output current | IOH | -2 | mA | 4 | |||
| Low-level output current | IOL | 20 | mA | 4 | |||
| Operating free-air temperature | TA | 0 | 70 | °C | SN74AS00 | 4 | |
| Input clamp voltage | VIK | -1.2 | V | VCC = 4.5 V, II = −18 mA | 4 | ||
| Low-level output voltage | VOL | 0.35 | 0.5 | V | VCC = 4.5 V, IOL = 20 mA | 4 | |
| Input current at maximum input voltage | II | 0.1 | mA | VCC = 5.5 V, VI = 7 V | 4 | ||
| High-level input current | IIH | 20 | µA | VCC = 5.5 V, VI = 2.7 V | 4 | ||
| Low-level input current | IIL | -0.5 | mA | VCC = 5.5 V, VI = 0.4 V | 4 | ||
| Output current | IO | -30 | -112 | mA | VCC = 5.5 V, VO = 2.25 V | 4 | |
| Supply current, output high | ICCH | 2 | 3.2 | mA | VCC = 5.5 V, VI = 0 | 4 | |
| Supply current, output low | ICCL | 10.8 | 17.4 | mA | VCC = 5.5 V, VI = 4.5 V | 4 | |
| Propagation delay time, low-to-high-level output | tPLH | 1 | 4.5 | ns | VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX | 4 | |
| Propagation delay time, high-to-low-level output | tPHL | 1 | 4 | ns | VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX | 4 | |
| Supply voltage | VCC | 7 | V | 2 | |||
| Input voltage | VI | 7 | V | 2 | |||
| Operating free-air temperature range | TA | 0 | 70 | °C | SN74AS00 | 4 | |
| Storage temperature range | Tstg | -65 | 150 | °C | 2 |
CAD (KiCad official)
- Symbol:
SN74AS00DR - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files:
sn74as00dr-etched.step/sn74as00dr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74as00dr.step/sn74as00dr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (25 pp, sha256
32079a6a07c77846, retrieved 2026-10-17, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# SN74AS00DR
**Texas Instruments** · Logic Gates · SOIC-14
SN74AS00DR from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Input A of gate 1, a 2-input positive NAND where Y = A • B; the absolute maximum input voltage is 7 V. |
| 2 | 1B | input | Input B of gate 1, a 2-input positive NAND where Y = A • B; the absolute maximum input voltage is 7 V. |
| 3 | 1Y | output | Output of gate 1 (Y = A • B); for SN74AS00 the recommended high-level output current is −2 mA and the low-level output current is 20 mA. |
| 4 | 2A | input | Input A of gate 2, a 2-input positive NAND where Y = A • B; the absolute maximum input voltage is 7 V. |
| 5 | 2B | input | Input B of gate 2, a 2-input positive NAND where Y = A • B; the absolute maximum input voltage is 7 V. |
| 6 | 2Y | output | Output of gate 2 (Y = A • B); for SN74AS00 the recommended high-level output current is −2 mA and the low-level output current is 20 mA. |
| 7 | GND | power_in | Ground reference pin of the device. |
| 8 | 3Y | output | Output of gate 3 (Y = A • B); for SN74AS00 the recommended high-level output current is −2 mA and the low-level output current is 20 mA. |
| 9 | 3A | input | Input A of gate 3, a 2-input positive NAND where Y = A • B; the absolute maximum input voltage is 7 V. |
| 10 | 3B | input | Input B of gate 3, a 2-input positive NAND where Y = A • B; the absolute maximum input voltage is 7 V. |
| 11 | 4Y | output | Output of gate 4 (Y = A • B); for SN74AS00 the recommended high-level output current is −2 mA and the low-level output current is 20 mA. |
| 12 | 4A | input | Input A of gate 4, a 2-input positive NAND where Y = A • B; the absolute maximum input voltage is 7 V. |
| 13 | 4B | input | Input B of gate 4, a 2-input positive NAND where Y = A • B; the absolute maximum input voltage is 7 V. |
| 14 | VCC | power_in | Supply voltage pin; recommended range 4.5 V to 5.5 V (nominal 5 V) with an absolute maximum of 7 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-14 |
| Category | Logic |
| Pins | 14 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | 4.5 | 5 | 5.5 | V | | 4 |
| High-level input voltage | VIH | 2 | | | V | | 4 |
| Low-level input voltage | VIL | | | 0.8 | V | | 4 |
| High-level output current | IOH | | | -2 | mA | | 4 |
| Low-level output current | IOL | | | 20 | mA | | 4 |
| Operating free-air temperature | TA | 0 | | 70 | °C | SN74AS00 | 4 |
| Input clamp voltage | VIK | | | -1.2 | V | VCC = 4.5 V, II = −18 mA | 4 |
| Low-level output voltage | VOL | | 0.35 | 0.5 | V | VCC = 4.5 V, IOL = 20 mA | 4 |
| Input current at maximum input voltage | II | | | 0.1 | mA | VCC = 5.5 V, VI = 7 V | 4 |
| High-level input current | IIH | | | 20 | µA | VCC = 5.5 V, VI = 2.7 V | 4 |
| Low-level input current | IIL | | | -0.5 | mA | VCC = 5.5 V, VI = 0.4 V | 4 |
| Output current | IO | -30 | | -112 | mA | VCC = 5.5 V, VO = 2.25 V | 4 |
| Supply current, output high | ICCH | | 2 | 3.2 | mA | VCC = 5.5 V, VI = 0 | 4 |
| Supply current, output low | ICCL | | 10.8 | 17.4 | mA | VCC = 5.5 V, VI = 4.5 V | 4 |
| Propagation delay time, low-to-high-level output | tPLH | 1 | | 4.5 | ns | VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX | 4 |
| Propagation delay time, high-to-low-level output | tPHL | 1 | | 4 | ns | VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX | 4 |
| Supply voltage | VCC | | | 7 | V | | 2 |
| Input voltage | VI | | | 7 | V | | 2 |
| Operating free-air temperature range | TA | 0 | | 70 | °C | SN74AS00 | 4 |
| Storage temperature range | Tstg | -65 | | 150 | °C | | 2 |
## CAD (KiCad official)
- Symbol: `SN74AS00DR`
- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`
- 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files: `sn74as00dr-etched.step` / `sn74as00dr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74as00dr.step` / `sn74as00dr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/sn74as00.pdf) (25 pp, sha256 `32079a6a07c77846`, retrieved 2026-10-17, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/sn74as00dr-datasheet.pdf)