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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

SN74ALVCH373PWR

Texas Instruments · Latches · TSSOP-20

SN74ALVCH373PWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	OE	input	Output-enable input; low level enables normal outputs, high level places outputs in high-impedance state.
2	1Q	tri_state	Q1 tri-state output; transparent to 1D input when LE is high, latched when LE transitions low.
3	1D	input	Data input 1 for latch 1; data state captured when LE transitions from high to low.
4	2D	input	Data input 2 for latch 2; data state captured when LE transitions from high to low.
5	2Q	tri_state	Q2 tri-state output; transparent to 2D input when LE is high, latched when LE transitions low.
6	3Q	tri_state	Q3 tri-state output; transparent to 3D input when LE is high, latched when LE transitions low.
7	3D	input	Data input 3 for latch 3; data state captured when LE transitions from high to low.
8	4D	input	Data input 4 for latch 4; data state captured when LE transitions from high to low.
9	4Q	tri_state	Q4 tri-state output; transparent to 4D input when LE is high, latched when LE transitions low.
10	GND	power_in	Ground; negative power supply rail.
11	LE	input	Latch-enable control input; high level enables transparent operation, low level latches Q outputs.
12	5Q	tri_state	Q5 tri-state output; transparent to 5D input when LE is high, latched when LE transitions low.
13	5D	input	Data input 5 for latch 5; data state captured when LE transitions from high to low.
14	6D	input	Data input 6 for latch 6; data state captured when LE transitions from high to low.
15	6Q	tri_state	Q6 tri-state output; transparent to 6D input when LE is high, latched when LE transitions low.
16	7Q	tri_state	Q7 tri-state output; transparent to 7D input when LE is high, latched when LE transitions low.
17	7D	input	Data input 7 for latch 7; data state captured when LE transitions from high to low.
18	8D	input	Data input 8 for latch 8; data state captured when LE transitions from high to low.
19	8Q	tri_state	Q8 tri-state output; transparent to 8D input when LE is high, latched when LE transitions low.
20	VCC	power_in	Supply voltage input; operates from 1.65 V to 3.6 V.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	TSSOP-20
Category	Logic
Pins	20

CAD (KiCad official)

Symbol: SN74ALVCH373PWR
Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
3D model: TSSOP-20 (KiCad packages3D, STEP)
3D model files: sn74alvch373pwr-etched.step / sn74alvch373pwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74alvch373pwr.step / sn74alvch373pwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (19 pp, sha256 2c1acfeac33a71b1, retrieved 2026-09-27, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF