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SN74ALVCH16825DL

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Texas Instruments Buffers / Drivers, SSOP-56-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogic icssn74alvch16825dlfactory-2.0.0extractor-text

Verified SN74ALVCH16825DL

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 56 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: SN74ALVCH16825DL · SSOP-56-300mil · 56 pins
  • ✓copper: 56 copper pads, none touching another net
  • ✓datasheet: all 56 pin names found in the 18-page datasheet
  • ✓distributor: lcsc C1548514, digikey 2156-SN74ALVCH16825DL-ND, mouser 595-SN74ALVCH16825DL
  • ✓family: SSOP-56_7.5x18.5mm_P0.635mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-v1_hcbq_/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 56 pins = 56 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 56 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ sn74alvch16825dl.kicad_sym✓ sn74alvch16825dl.kicad_mod✓ sn74alvch16825dl.step
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SN74ALVCH16825DL

Texas Instruments · Buffers / Drivers · SSOP-56-300mil

SN74ALVCH16825DL from Texas Instruments, in a SSOP-56-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1OE1 input Active-low output enable for the first 9-bit section (1Y1-1Y9); if this input is high, all nine 1Y outputs go to high impedance.
2 1Y1 tri_state 3-state output of channel 1 in the first 9-bit section, high impedance when either 1OE1 or 1OE2 is high.
3 1Y2 tri_state 3-state output of channel 2 in the first 9-bit section, high impedance when either 1OE1 or 1OE2 is high.
4 GND power_in Ground reference pin.
5 1Y3 tri_state 3-state output of channel 3 in the first 9-bit section, high impedance when either 1OE1 or 1OE2 is high.
6 1Y4 tri_state 3-state output of channel 4 in the first 9-bit section, high impedance when either 1OE1 or 1OE2 is high.
7 VCC power_in Supply voltage; the device is designed for 1.65 V to 3.6 V VCC operation.
8 1Y5 tri_state 3-state output of channel 5 in the first 9-bit section, high impedance when either 1OE1 or 1OE2 is high.
9 1Y6 tri_state 3-state output of channel 6 in the first 9-bit section, high impedance when either 1OE1 or 1OE2 is high.
10 1Y7 tri_state 3-state output of channel 7 in the first 9-bit section, high impedance when either 1OE1 or 1OE2 is high.
11 GND power_in Ground reference pin.
12 1Y8 tri_state 3-state output of channel 8 in the first 9-bit section, high impedance when either 1OE1 or 1OE2 is high.
13 1Y9 tri_state 3-state output of channel 9 in the first 9-bit section, high impedance when either 1OE1 or 1OE2 is high.
14 GND power_in Ground reference pin.
15 GND power_in Ground reference pin.
16 2Y1 tri_state 3-state output of channel 1 in the second 9-bit section, high impedance when either 2OE1 or 2OE2 is high.
17 2Y2 tri_state 3-state output of channel 2 in the second 9-bit section, high impedance when either 2OE1 or 2OE2 is high.
18 GND power_in Ground reference pin.
19 2Y3 tri_state 3-state output of channel 3 in the second 9-bit section, high impedance when either 2OE1 or 2OE2 is high.
20 2Y4 tri_state 3-state output of channel 4 in the second 9-bit section, high impedance when either 2OE1 or 2OE2 is high.
21 2Y5 tri_state 3-state output of channel 5 in the second 9-bit section, high impedance when either 2OE1 or 2OE2 is high.
22 VCC power_in Supply voltage; the device is designed for 1.65 V to 3.6 V VCC operation.
23 2Y6 tri_state 3-state output of channel 6 in the second 9-bit section, high impedance when either 2OE1 or 2OE2 is high.
24 2Y7 tri_state 3-state output of channel 7 in the second 9-bit section, high impedance when either 2OE1 or 2OE2 is high.
25 GND power_in Ground reference pin.
26 2Y8 tri_state 3-state output of channel 8 in the second 9-bit section, high impedance when either 2OE1 or 2OE2 is high.
27 2Y9 tri_state 3-state output of channel 9 in the second 9-bit section, high impedance when either 2OE1 or 2OE2 is high.
28 2OE1 input Active-low output enable for the second 9-bit section (2Y1-2Y9); if this input is high, all nine 2Y outputs go to high impedance.
29 2OE2 input Active-low output enable for the second 9-bit section (2Y1-2Y9); if this input is high, all nine 2Y outputs go to high impedance.
30 2A9 input Data input for channel 9 of the second 9-bit section; bus hold holds unused or floating inputs at a valid logic level.
31 2A8 input Data input for channel 8 of the second 9-bit section; bus hold holds unused or floating inputs at a valid logic level.
32 GND power_in Ground reference pin.
33 2A7 input Data input for channel 7 of the second 9-bit section; bus hold holds unused or floating inputs at a valid logic level.
34 2A6 input Data input for channel 6 of the second 9-bit section; bus hold holds unused or floating inputs at a valid logic level.
35 VCC power_in Supply voltage; the device is designed for 1.65 V to 3.6 V VCC operation.
36 2A5 input Data input for channel 5 of the second 9-bit section; bus hold holds unused or floating inputs at a valid logic level.
37 2A4 input Data input for channel 4 of the second 9-bit section; bus hold holds unused or floating inputs at a valid logic level.
38 2A3 input Data input for channel 3 of the second 9-bit section; bus hold holds unused or floating inputs at a valid logic level.
39 GND power_in Ground reference pin.
40 2A2 input Data input for channel 2 of the second 9-bit section; bus hold holds unused or floating inputs at a valid logic level.
41 2A1 input Data input for channel 1 of the second 9-bit section; bus hold holds unused or floating inputs at a valid logic level.
42 GND power_in Ground reference pin.
43 GND power_in Ground reference pin.
44 1A9 input Data input for channel 9 of the first 9-bit section; bus hold holds unused or floating inputs at a valid logic level.
45 1A8 input Data input for channel 8 of the first 9-bit section; bus hold holds unused or floating inputs at a valid logic level.
46 GND power_in Ground reference pin.
47 1A7 input Data input for channel 7 of the first 9-bit section; bus hold holds unused or floating inputs at a valid logic level.
48 1A6 input Data input for channel 6 of the first 9-bit section; bus hold holds unused or floating inputs at a valid logic level.
49 1A5 input Data input for channel 5 of the first 9-bit section; bus hold holds unused or floating inputs at a valid logic level.
50 VCC power_in Supply voltage; the device is designed for 1.65 V to 3.6 V VCC operation.
51 1A4 input Data input for channel 4 of the first 9-bit section; bus hold holds unused or floating inputs at a valid logic level.
52 1A3 input Data input for channel 3 of the first 9-bit section; bus hold holds unused or floating inputs at a valid logic level.
53 GND power_in Ground reference pin.
54 1A2 input Data input for channel 2 of the first 9-bit section; bus hold holds unused or floating inputs at a valid logic level.
55 1A1 input Data input for channel 1 of the first 9-bit section; bus hold holds unused or floating inputs at a valid logic level.
56 1OE2 input Active-low output enable for the first 9-bit section (1Y1-1Y9); if this input is high, all nine 1Y outputs go to high impedance.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SSOP-56-300mil
Category Logic ICs
Pins 56

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 1.65 3.6 V 3
High-level input voltage VIH 1.7 V VCC = 2.3 V to 2.7 V 3
High-level input voltage VIH 2 V VCC = 2.7 V to 3.6 V 3
Low-level input voltage VIL 0.7 V VCC = 2.3 V to 2.7 V 3
Low-level input voltage VIL 0.8 V VCC = 2.7 V to 3.6 V 3
Input voltage VI 0 V 3
Output voltage VO 0 V 3
High-level output current IOH -4 mA VCC = 1.65 V 3
High-level output current IOH -12 mA VCC = 2.3 V 3
High-level output current IOH -24 mA VCC = 3 V 3
Low-level output current IOL 4 mA VCC = 1.65 V 3
Low-level output current IOL 12 mA VCC = 2.3 V 3
Low-level output current IOL 24 mA VCC = 3 V 3
Input transition rise or fall rate ∆t/∆v 10 ns/V 3
Operating free-air temperature TA -40 85 °C 3
Supply voltage range VCC -0.5 4.6 V 3
Input voltage range VI -0.5 4.6 V 3
Output voltage range VO -0.5 V upper limit printed as VCC + 0.5 V 3
Input clamp current IIK -50 mA VI < 0 3
Output clamp current IOK -50 mA VO < 0 3
Continuous output current IO -50 50 mA 3
Continuous current through each VCC or GND -100 100 mA 3
Storage temperature range Tstg -65 150 °C 3
Package thermal impedance θJA 74 °C/W DL package 3
High-level output voltage VOH 1.2 V IOH = -4 mA, VCC = 1.65 V 4
High-level output voltage VOH 2 V IOH = -6 mA, VCC = 2.3 V 4
High-level output voltage VOH 1.7 V IOH = -12 mA, VCC = 2.3 V 4
High-level output voltage VOH 2.2 V IOH = -12 mA, VCC = 2.7 V 4
High-level output voltage VOH 2.4 V IOH = -12 mA, VCC = 3 V 4
Low-level output voltage VOL 0.2 V IOL = 100 µA, VCC = 1.65 V to 3.6 V 4
Low-level output voltage VOL 0.45 V IOL = 4 mA, VCC = 1.65 V 4
Low-level output voltage VOL 0.4 V IOL = 6 mA, VCC = 2.3 V 4
Low-level output voltage VOL 0.7 V IOL = 12 mA, VCC = 2.3 V 4
Low-level output voltage VOL 0.55 V IOL = 24 mA, VCC = 3 V 4
Input current II -5 5 µA VI = VCC or GND, VCC = 3.6 V 4
Bus-hold current I(hold) 25 µA VI = 0.58 V, VCC = 1.65 V 4
Bus-hold current I(hold) -25 µA VI = 1.07 V, VCC = 1.65 V 4
Bus-hold current I(hold) 45 µA VI = 0.7 V, VCC = 2.3 V 4
Bus-hold current I(hold) -45 µA VI = 1.7 V, VCC = 2.3 V 4
Bus-hold current I(hold) 75 µA VI = 0.8 V, VCC = 3 V 4
Bus-hold current I(hold) -75 µA VI = 2 V, VCC = 3 V 4
Bus-hold maximum dynamic current I(hold) -500 500 µA VI = 0 to 3.6 V, VCC = 3.6 V 4
Off-state output current IOZ -10 10 µA VO = VCC or GND, VCC = 3.6 V 4
Supply current ICC 40 µA VI = VCC or GND, IO = 0, VCC = 3.6 V 4
Additional supply current per input ∆ICC 750 µA One input at VCC - 0.6 V, other inputs at VCC or GND, VCC = 3 V to 3.6 V 4

CAD (KiCad official)

  • Symbol: SN74ALVCH16825DL
  • Footprint: Package_SO:SSOP-56_7.5x18.5mm_P0.635mm
  • 3D model: SSOP-56-300mil (KiCad packages3D, STEP)
  • 3D model files: sn74alvch16825dl-etched.step / sn74alvch16825dl-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74alvch16825dl.step / sn74alvch16825dl.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (18 pp, sha256 d517cc195c706864, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF