# SN74ALVCH16721DLR

**Texas Instruments** · Flip Flops · SSOP-56-300mil

SN74ALVCH16721DLR from Texas Instruments, in a SSOP-56-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OE | input | Buffered output enable that puts the 20 outputs in a normal logic state or high-impedance state; tie to VCC through a pullup resistor to ensure high-impedance during power up or power down. |
| 2 | Q1 | tri_state | 3-state output of flip-flop 1. |
| 3 | Q2 | tri_state | 3-state output of flip-flop 2. |
| 4 | GND | power_in | Ground; continuous current through each VCC or GND is limited to ±100 mA. |
| 5 | Q3 | tri_state | 3-state output of flip-flop 3. |
| 6 | Q4 | tri_state | 3-state output of flip-flop 4. |
| 7 | VCC | power_in | Supply voltage, 1.65 V to 3.6 V recommended. |
| 8 | Q5 | tri_state | 3-state output of flip-flop 5. |
| 9 | Q6 | tri_state | 3-state output of flip-flop 6. |
| 10 | Q7 | tri_state | 3-state output of flip-flop 7. |
| 11 | GND | power_in | Ground; continuous current through each VCC or GND is limited to ±100 mA. |
| 12 | Q8 | tri_state | 3-state output of flip-flop 8. |
| 13 | Q9 | tri_state | 3-state output of flip-flop 9. |
| 14 | Q10 | tri_state | 3-state output of flip-flop 10. |
| 15 | Q11 | tri_state | 3-state output of flip-flop 11. |
| 16 | Q12 | tri_state | 3-state output of flip-flop 12. |
| 17 | Q13 | tri_state | 3-state output of flip-flop 13. |
| 18 | GND | power_in | Ground; continuous current through each VCC or GND is limited to ±100 mA. |
| 19 | Q14 | tri_state | 3-state output of flip-flop 14. |
| 20 | Q15 | tri_state | 3-state output of flip-flop 15. |
| 21 | Q16 | tri_state | 3-state output of flip-flop 16. |
| 22 | VCC | power_in | Supply voltage, 1.65 V to 3.6 V recommended. |
| 23 | Q17 | tri_state | 3-state output of flip-flop 17. |
| 24 | Q18 | tri_state | 3-state output of flip-flop 18. |
| 25 | GND | power_in | Ground; continuous current through each VCC or GND is limited to ±100 mA. |
| 26 | Q19 | tri_state | 3-state output of flip-flop 19. |
| 27 | Q20 | tri_state | 3-state output of flip-flop 20. |
| 28 | NC | unconnected | No internal connection. |
| 29 | CLKEN | input | Clock enable; when low, data is stored on the positive CLK transition, and when high no data is stored. |
| 30 | D20 | input | Data input for flip-flop 20 with bus hold. |
| 31 | D19 | input | Data input for flip-flop 19 with bus hold. |
| 32 | GND | power_in | Ground; continuous current through each VCC or GND is limited to ±100 mA. |
| 33 | D18 | input | Data input for flip-flop 18 with bus hold. |
| 34 | D17 | input | Data input for flip-flop 17 with bus hold. |
| 35 | VCC | power_in | Supply voltage, 1.65 V to 3.6 V recommended. |
| 36 | D16 | input | Data input for flip-flop 16 with bus hold. |
| 37 | D15 | input | Data input for flip-flop 15 with bus hold. |
| 38 | D14 | input | Data input for flip-flop 14 with bus hold. |
| 39 | GND | power_in | Ground; continuous current through each VCC or GND is limited to ±100 mA. |
| 40 | D13 | input | Data input for flip-flop 13 with bus hold. |
| 41 | D12 | input | Data input for flip-flop 12 with bus hold. |
| 42 | D11 | input | Data input for flip-flop 11 with bus hold. |
| 43 | D10 | input | Data input for flip-flop 10 with bus hold. |
| 44 | D9 | input | Data input for flip-flop 9 with bus hold. |
| 45 | D8 | input | Data input for flip-flop 8 with bus hold. |
| 46 | GND | power_in | Ground; continuous current through each VCC or GND is limited to ±100 mA. |
| 47 | D7 | input | Data input for flip-flop 7 with bus hold. |
| 48 | D6 | input | Data input for flip-flop 6 with bus hold. |
| 49 | D5 | input | Data input for flip-flop 5 with bus hold. |
| 50 | VCC | power_in | Supply voltage, 1.65 V to 3.6 V recommended. |
| 51 | D4 | input | Data input for flip-flop 4 with bus hold. |
| 52 | D3 | input | Data input for flip-flop 3 with bus hold. |
| 53 | GND | power_in | Ground; continuous current through each VCC or GND is limited to ±100 mA. |
| 54 | D2 | input | Data input for flip-flop 2 with bus hold. |
| 55 | D1 | input | Data input for flip-flop 1 with bus hold. |
| 56 | CLK | input | Clock input; data is stored on the positive transition when CLKEN is low. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SSOP-56-300mil |
| Category | Logic |
| Pins | 56 |

## CAD (KiCad official)

- Symbol: `SN74ALVCH16721DLR`
- Footprint: `Package_SO:SSOP-56_7.5x18.5mm_P0.635mm`
- 3D model: SSOP-56-300mil (KiCad packages3D, STEP)
- 3D model files: `sn74alvch16721dlr-etched.step` / `sn74alvch16721dlr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74alvch16721dlr.step` / `sn74alvch16721dlr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/sn74alvch16721) (18 pp, sha256 `dec914c4a56319a2`, retrieved 2026-10-07, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/sn74alvch16721dlr-datasheet.pdf)