component
SN74ALVC244PWR
Public Made by Adomby adom
Texas Instruments Buffers, Drivers, Receivers, Transceivers, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 5d ago |
| viewers | 5d ago |
| package.json | 5d ago |
| page.json | 5d ago |
| README.md | 5d ago |
| sn74alvc244pwr-etched.glb | 5d ago |
| sn74alvc244pwr-etched.step | 5d ago |
| sn74alvc244pwr-hero.glb | 5d ago |
| sn74alvc244pwr-hero.overlay.json | 5d ago |
| sn74alvc244pwr.glb | 5d ago |
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| sn74alvc244pwr.step | 5d ago |
SN74ALVC244PWR
Texas Instruments · Buffers, Drivers, Receivers, Transceivers · TSSOP-20
SN74ALVC244PWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1OE | input | Output enable for buffer bank 1, active low: when low the device passes data from the A inputs to the Y outputs, and when high the outputs are in the high-impedance state. |
| 2 | 1A1 | input | Data input 1A1 of bank 1 (line driver channel 1). |
| 3 | 2Y4 | output | 3-state data output 2Y4 of bank 2 (line driver channel 4), high-impedance when 2OE is high. |
| 4 | 1A2 | input | Data input 1A2 of bank 1 (line driver channel 2). |
| 5 | 2Y3 | output | 3-state data output 2Y3 of bank 2 (line driver channel 3), high-impedance when 2OE is high. |
| 6 | 1A3 | input | Data input 1A3 of bank 1 (line driver channel 3). |
| 7 | 2Y2 | output | 3-state data output 2Y2 of bank 2 (line driver channel 2), high-impedance when 2OE is high. |
| 8 | 1A4 | input | Data input 1A4 of bank 1 (line driver channel 4). |
| 9 | 2Y1 | output | 3-state data output 2Y1 of bank 2 (line driver channel 1), high-impedance when 2OE is high. |
| 10 | GND | power_in | Ground reference for the device. |
| 11 | 2A1 | input | Data input 2A1 of bank 2 (line driver channel 1). |
| 12 | 1Y4 | output | 3-state data output 1Y4 of bank 1 (line driver channel 4), high-impedance when 1OE is high. |
| 13 | 2A2 | input | Data input 2A2 of bank 2 (line driver channel 2). |
| 14 | 1Y3 | output | 3-state data output 1Y3 of bank 1 (line driver channel 3), high-impedance when 1OE is high. |
| 15 | 2A3 | input | Data input 2A3 of bank 2 (line driver channel 3). |
| 16 | 1Y2 | output | 3-state data output 1Y2 of bank 1 (line driver channel 2), high-impedance when 1OE is high. |
| 17 | 2A4 | input | Data input 2A4 of bank 2 (line driver channel 4). |
| 18 | 1Y1 | output | 3-state data output 1Y1 of bank 1 (line driver channel 1), high-impedance when 1OE is high. |
| 19 | 2OE | input | Output enable for buffer bank 2, active low: when low the device passes data from the A inputs to the Y outputs, and when high the outputs are in the high-impedance state. |
| 20 | VCC | power_in | Supply voltage, 1.65 V to 3.6 V; unused inputs must be held at VCC or GND. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-20 |
| Category | Logic |
| Pins | 20 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | 1.65 | 3.6 | V | 3 | ||
| High-level input voltage | VIH | 1.7 | V | VCC = 2.3 V to 2.7 V | 3 | ||
| High-level input voltage | VIH | 2 | V | VCC = 2.7 V to 3.6 V | 3 | ||
| Low-level input voltage | VIL | 0.7 | V | VCC = 2.3 V to 2.7 V | 3 | ||
| Low-level input voltage | VIL | 0.8 | V | VCC = 2.7 V to 3.6 V | 3 | ||
| Input voltage | VI | 0 | 3.6 | V | 3 | ||
| High-level output current | IOH | -4 | mA | VCC = 1.65 V | 3 | ||
| High-level output current | IOH | -12 | mA | VCC = 2.3 V | 3 | ||
| High-level output current | IOH | -24 | mA | VCC = 3 V | 3 | ||
| Low-level output current | IOL | 4 | mA | VCC = 1.65 V | 3 | ||
| Low-level output current | IOL | 12 | mA | VCC = 2.3 V | 3 | ||
| Low-level output current | IOL | 24 | mA | VCC = 3 V | 3 | ||
| Input transition rise or fall rate | ∆t/∆v | 5 | ns/V | 3 | |||
| Operating free-air temperature | TA | -40 | 85 | °C | 3 | ||
| Supply voltage range | VCC | -0.5 | 4.6 | V | 2 | ||
| Input voltage range | VI | -0.5 | 4.6 | V | 2 | ||
| Input clamp current | IIK | -50 | mA | VI < 0 | 2 | ||
| Output clamp current | IOK | -50 | mA | VO < 0 | 2 | ||
| Continuous output current | IO | -50 | 50 | mA | 2 | ||
| Continuous current through VCC or GND | -100 | 100 | mA | 2 | |||
| Storage temperature range | Tstg | -65 | 150 | °C | 2 | ||
| High-level output voltage | VOH | 1.2 | V | IOH = -4 mA; VCC = 1.65 V | 3 | ||
| High-level output voltage | VOH | 2 | V | IOH = -6 mA; VCC = 2.3 V | 3 | ||
| High-level output voltage | VOH | 1.7 | V | IOH = -12 mA; VCC = 2.3 V | 3 | ||
| High-level output voltage | VOH | 2.2 | V | IOH = -12 mA; VCC = 2.7 V | 3 | ||
| High-level output voltage | VOH | 2.4 | V | IOH = -12 mA; VCC = 3 V | 3 | ||
| Low-level output voltage | VOL | 0.2 | V | IOL = 100 µA; VCC = 1.65 V to 3.6 V | 3 | ||
| Low-level output voltage | VOL | 0.45 | V | IOL = 4 mA; VCC = 1.65 V | 3 | ||
| Low-level output voltage | VOL | 0.4 | V | IOL = 6 mA; VCC = 2.3 V | 3 | ||
| Low-level output voltage | VOL | 0.7 | V | IOL = 12 mA; VCC = 2.3 V | 3 | ||
| Low-level output voltage | VOL | 0.55 | V | IOL = 24 mA; VCC = 3 V | 3 | ||
| Input leakage current | II | -5 | 5 | µA | VI = VCC or GND; VCC = 3.6 V | 3 | |
| Off-state output current | IOZ | -10 | 10 | µA | VO = VCC or GND; VCC = 3.6 V | 3 | |
| Quiescent supply current | ICC | 10 | µA | VI = VCC or GND, IO = 0; VCC = 3.6 V | 3 | ||
| Additional quiescent supply current per input | ∆ICC | 750 | µA | One input at VCC - 0.6 V, other inputs at VCC or GND; VCC = 3 V to 3.6 V | 3 | ||
| Propagation delay A to Y | tpd | 1 | 4.4 | ns | VCC = 1.8 V ± 0.15 V; see Figure 1 | 4 | |
| Propagation delay A to Y | tpd | 1 | 3.1 | ns | VCC = 2.5 V ± 0.2 V; see Figure 1 | 4 | |
| Propagation delay A to Y | tpd | 1.1 | 2.8 | ns | VCC = 3.3 V ± 0.3 V; see Figure 1 | 4 | |
| Enable time OE to Y | ten | 1.8 | 6.9 | ns | VCC = 1.8 V ± 0.15 V; see Figure 1 | 4 | |
| Enable time OE to Y | ten | 1.5 | 5.4 | ns | VCC = 2.5 V ± 0.2 V; see Figure 1 | 4 | |
| Enable time OE to Y | ten | 1.5 | 4.5 | ns | VCC = 3.3 V ± 0.3 V; see Figure 1 | 4 | |
| Disable time OE to Y | tdis | 1.8 | 5.9 | ns | VCC = 1.8 V ± 0.15 V; see Figure 1 | 4 | |
| Disable time OE to Y | tdis | 1 | 4.1 | ns | VCC = 2.5 V ± 0.2 V; see Figure 1 | 4 | |
| Disable time OE to Y | tdis | 1.7 | 4.2 | ns | VCC = 3.3 V ± 0.3 V; see Figure 1 | 4 | |
| Package thermal impedance, PW package | θJA | 83 | °C/W | PW package, per JESD 51-7 | 2 |
CAD (KiCad official)
- Symbol:
SN74ALVC244PWR - Footprint:
Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm - 3D model: TSSOP-20 (KiCad packages3D, STEP)
- 3D model files:
sn74alvc244pwr-etched.step/sn74alvc244pwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74alvc244pwr.step/sn74alvc244pwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (20 pp, sha256
8ab24c38bc72c4c5, retrieved 2026-10-18, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).