component
SN74ALS873BDWR
Public Made by Adomby adom
Texas Instruments Latches, SOIC-24-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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{
"schema_version": 1,
"type": "component",
"slug": "sn74als873bdwr",
"title": "SN74ALS873BDWR",
"brief": "Texas Instruments Latches, SOIC-24-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
"version": "0.1.0",
"license": "CC-BY-SA-4.0",
"tags": [
"component",
"logic",
"sn74als873bdwr",
"factory-2.0.0",
"extractor-text"
],
"component": {
"mpn": "SN74ALS873BDWR",
"manufacturer": "Texas Instruments",
"package": "SOIC-24-300mil",
"pin_count": 24,
"category": "Logic",
"subcategory": "Latches",
"datasheet": "https://www.ti.com/cn/lit/gpn/sn54als873b",
"parts": {
"symbol": "sn74als873bdwr.kicad_sym",
"footprint": "sn74als873bdwr.kicad_mod",
"model_3d": "sn74als873bdwr-hero.glb",
"model_3d_plain": "sn74als873bdwr.glb",
"model_3d_step": "sn74als873bdwr-etched.step",
"model_3d_step_plain": "sn74als873bdwr.step",
"lbr": "sn74als873bdwr.lbr"
},
"distributor_links": {
"lcsc": "C2675408",
"digikey": "296-29550-2-ND",
"mouser": "595-SN74ALS873BDWR"
},
"distributor_check": {
"checked_at": "2026-10-08T16:07:16Z",
"source": "Component Ocean /api/assign-pns",
"digikey": {
"pn": "296-29550-2-ND",
"status": "found",
"lifecycle": "Active"
},
"mouser": {
"pn": "595-SN74ALS873BDWR",
"status": "found"
}
},
"pins": [
{
"number": "1",
"name": "1CLR",
"type": "input",
"description": "Active-low clear for latch group 1; when low, the 1Q outputs go low independently of 1LE."
},
{
"number": "2",
"name": "1OE",
"type": "input",
"description": "Output enable for latch group 1; when at a high logic level, the 1Q outputs are forced to the high-impedance state."
},
{
"number": "3",
"name": "1D1",
"type": "input",
"description": "Data input for bit 1 of latch group 1; while 1LE is high the 1Q output follows this input, and it is latched when 1LE goes low (setup 10 ns, hold 7 ns)."
},
{
"number": "4",
"name": "1D2",
"type": "input",
"description": "Data input for bit 2 of latch group 1; while 1LE is high the 1Q output follows this input, and it is latched when 1LE goes low (setup 10 ns, hold 7 ns)."
},
{
"number": "5",
"name": "1D3",
"type": "input",
"description": "Data input for bit 3 of latch group 1; while 1LE is high the 1Q output follows this input, and it is latched when 1LE goes low (setup 10 ns, hold 7 ns)."
},
{
"number": "6",
"name": "1D4",
"type": "input",
"description": "Data input for bit 4 of latch group 1; while 1LE is high the 1Q output follows this input, and it is latched when 1LE goes low (setup 10 ns, hold 7 ns)."
},
{
"number": "7",
"name": "2D1",
"type": "input",
"description": "Data input for bit 1 of latch group 2; while 2LE is high the 2Q output follows this input, and it is latched when 2LE goes low (setup 10 ns, hold 7 ns)."
},
{
"number": "8",
"name": "2D2",
"type": "input",
"description": "Data input for bit 2 of latch group 2; while 2LE is high the 2Q output follows this input, and it is latched when 2LE goes low (setup 10 ns, hold 7 ns)."
},
{
"number": "9",
"name": "2D3",
"type": "input",
"description": "Data input for bit 3 of latch group 2; while 2LE is high the 2Q output follows this input, and it is latched when 2LE goes low (setup 10 ns, hold 7 ns)."
},
{
"number": "10",
"name": "2D4",
"type": "input",
"description": "Data input for bit 4 of latch group 2; while 2LE is high the 2Q output follows this input, and it is latched when 2LE goes low (setup 10 ns, hold 7 ns)."
},
{
"number": "11",
"name": "2OE",
"type": "input",
"description": "Output enable for latch group 2; when at a high logic level, the 2Q outputs are forced to the high-impedance state."
},
{
"number": "12",
"name": "GND",
"type": "power_in",
"description": "Ground reference pin for the device."
},
{
"number": "13",
"name": "2CLR",
"type": "input",
"description": "Active-low clear for latch group 2; when low, the 2Q outputs go low independently of 2LE."
},
{
"number": "14",
"name": "2LE",
"type": "input",
"description": "Latch enable for group 2; while high the 2Q outputs follow the D inputs, and when low the outputs are latched."
},
{
"number": "15",
"name": "2Q4",
"type": "tri_state",
"description": "Bit 4 3-state buffer output of latch group 2, designed to drive bus lines directly."
},
{
"number": "16",
"name": "2Q3",
"type": "tri_state",
"description": "Bit 3 3-state buffer output of latch group 2, designed to drive bus lines directly."
},
{
"number": "17",
"name": "2Q2",
"type": "tri_state",
"description": "Bit 2 3-state buffer output of latch group 2, designed to drive bus lines directly."
},
{
"number": "18",
"name": "2Q1",
"type": "tri_state",
"description": "Bit 1 3-state buffer output of latch group 2, designed to drive bus lines directly."
},
{
"number": "19",
"name": "1Q4",
"type": "tri_state",
"description": "Bit 4 3-state buffer output of latch group 1, designed to drive bus lines directly."
},
{
"number": "20",
"name": "1Q3",
"type": "tri_state",
"description": "Bit 3 3-state buffer output of latch group 1, designed to drive bus lines directly."
},
{
"number": "21",
"name": "1Q2",
"type": "tri_state",
"description": "Bit 2 3-state buffer output of latch group 1, designed to drive bus lines directly."
},
{
"number": "22",
"name": "1Q1",
"type": "tri_state",
"description": "Bit 1 3-state buffer output of latch group 1, designed to drive bus lines directly."
},
{
"number": "23",
"name": "1LE",
"type": "input",
"description": "Latch enable for group 1; while high the 1Q outputs follow the D inputs, and when low the outputs are latched."
},
{
"number": "24",
"name": "VCC",
"type": "power_in",
"description": "Supply voltage, recommended 4.5 V to 5.5 V with 5 V nominal (absolute maximum 7 V)."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
"factory_chain": {
"factory": "2.0.0",
"extractor": "extract_pins 0.3",
"primary_model": "claude-haiku-5-5",
"primary_mode": "text",
"consensus_model": "claude-sonnet-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: Pin numbers are taken from the logic symbol annotations on page 2 (\"Pin numbers shown are for the DW; The datasheet lists the SN74ALS873B DW package as 24-pin SOIC; the package addendum (page 8) confirm; Ground and clear/enable descriptions are limited to what the datasheet states; the datasheet gives n"
],
"pages_sent": 15,
"cost_usd": 0.0817,
"at": "2026-10-08T16:06:46"
},
"datasheet": {
"url": "https://www.ti.com/cn/lit/gpn/sn54als873b",
"pages": 15,
"sha256": "7a37dd6b1e3368fa",
"source_tier": "lcsc"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 24,
"described": 24,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
"viewers": {
"symbol": "viewers/symbol.html",
"footprint": "viewers/footprint.html"
},
"models_3d": [
{
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"role": "plain",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
10.3,
15.4,
2.75
],
"zmin_mm": 0,
"centre_offset_mm": 0,
"footprint_binding": "identity",
"sha256": "4b0d20f82f5b0124fecfe11c941274a3c865a30f7baee8b8fadd7df55972d4cd",
"checked": "2026-10-08",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
},
{
"file": "sn74als873bdwr-etched.step",
"role": "eda",
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"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
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"zmin_mm": 0,
"centre_offset_mm": 0,
"footprint_binding": "identity",
"sha256": "299156769cbc0cef366b2931d78d12a7940dacfb5db3d41a847faac0c2ef3c72",
"checked": "2026-10-08",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
}
]
},
"metadata": {
"specs": {
"Manufacturer": "Texas Instruments",
"Package": "SOIC-24-300mil",
"Category": "Logic",
"Pins": "24"
}
},
"variants": [],
"sections": [
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"viewers",
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"discovery_triggers": [
"sn74als873bdwr"
],
"discovery_pitch": "SN74ALS873BDWR (Texas Instruments) component page: datasheet pinout, KiCad symbol, footprint and 3D.",
"author": {
"name": "Ray",
"email": "[email protected]"
},
"dependencies": {},
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"files": [
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