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SN74ALS74ADR

Public Made by Adom

by adom

Texas Instruments Flip Flops, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
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docs sn74als74adr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
viewers sn74als74adr: viewers · Ray 5d ago
package.json Publish 0.1.0 · Ray 5d ago
page.json Set visibility: public · Ray 5d ago
README.md Initial commit: component/sn74als74adr · Ray 5d ago
sn74als74adr-etched.fit.json sn74als74adr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
sn74als74adr-etched.glb sn74als74adr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
sn74als74adr-etched.step sn74als74adr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
sn74als74adr.glb Publish 0.1.0 · Ray 5d ago
sn74als74adr.kicad_mod Publish 0.1.0 · Ray 5d ago
sn74als74adr.kicad_sym Publish 0.1.0 · Ray 5d ago
sn74als74adr.lbr Publish 0.1.0 · Ray 5d ago
sn74als74adr.step Publish 0.1.0 · Ray 5d ago

SN74ALS74ADR

Texas Instruments · Flip Flops · SOIC-14

SN74ALS74ADR from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1CLR input Flip-flop 1 clear input; a low level resets the outputs regardless of the other inputs.
2 1D input Flip-flop 1 data input; transferred to the outputs on the positive-going clock edge when PRE and CLR are high.
3 1CLK input Flip-flop 1 clock input, positive-edge triggered at a voltage level and not directly related to the rise time.
4 1PRE input Flip-flop 1 preset input; a low level sets the outputs regardless of the other inputs.
5 1Q output Flip-flop 1 true output.
6 1Q̅ output Flip-flop 1 complementary output.
7 GND power_in Ground.
8 2Q̅ output Flip-flop 2 complementary output.
9 2Q output Flip-flop 2 true output.
10 2PRE input Flip-flop 2 preset input; a low level sets the outputs regardless of the other inputs.
11 2CLK input Flip-flop 2 clock input, positive-edge triggered at a voltage level and not directly related to the rise time.
12 2D input Flip-flop 2 data input; transferred to the outputs on the positive-going clock edge when PRE and CLR are high.
13 2CLR input Flip-flop 2 clear input; a low level resets the outputs regardless of the other inputs.
14 VCC power_in Supply voltage, 4.5 V to 5.5 V recommended (7 V absolute maximum).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-14
Category Logic
Pins 14

CAD (KiCad official)

  • Symbol: SN74ALS74ADR
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOIC-14 (KiCad packages3D, STEP)
  • 3D model files: sn74als74adr-etched.step / sn74als74adr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74als74adr.step / sn74als74adr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (23 pp, sha256 3b44b22e26026ae1, retrieved 2026-09-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF