component
SN74ALS74ADR
Public Made by Adomby adom
Texas Instruments Flip Flops, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+50@@ -0,0 +1,50 @@+# SN74ALS74ADR++**Texas Instruments** · Flip Flops · SOIC-14++SN74ALS74ADR from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | 1CLR | input | Flip-flop 1 clear input; a low level resets the outputs regardless of the other inputs. |+| 2 | 1D | input | Flip-flop 1 data input; transferred to the outputs on the positive-going clock edge when PRE and CLR are high. |+| 3 | 1CLK | input | Flip-flop 1 clock input, positive-edge triggered at a voltage level and not directly related to the rise time. |+| 4 | 1PRE | input | Flip-flop 1 preset input; a low level sets the outputs regardless of the other inputs. |+| 5 | 1Q | output | Flip-flop 1 true output. |+| 6 | 1Q̅ | output | Flip-flop 1 complementary output. |+| 7 | GND | power_in | Ground. |+| 8 | 2Q̅ | output | Flip-flop 2 complementary output. |+| 9 | 2Q | output | Flip-flop 2 true output. |+| 10 | 2PRE | input | Flip-flop 2 preset input; a low level sets the outputs regardless of the other inputs. |+| 11 | 2CLK | input | Flip-flop 2 clock input, positive-edge triggered at a voltage level and not directly related to the rise time. |+| 12 | 2D | input | Flip-flop 2 data input; transferred to the outputs on the positive-going clock edge when PRE and CLR are high. |+| 13 | 2CLR | input | Flip-flop 2 clear input; a low level resets the outputs regardless of the other inputs. |+| 14 | VCC | power_in | Supply voltage, 4.5 V to 5.5 V recommended (7 V absolute maximum). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-14 |+| Category | Logic |+| Pins | 14 |++## CAD (KiCad official)++- Symbol: `SN74ALS74ADR`+- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`+- 3D model: SOIC-14 (KiCad packages3D, STEP)+- 3D model files: `sn74als74adr-etched.step` / `sn74als74adr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74als74adr.step` / `sn74als74adr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/sn74als74a.pdf) (23 pp, sha256 `3b44b22e26026ae1`, retrieved 2026-09-30, tier: manufacturer)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/sn74als74adr-datasheet.pdf)
page.jsonadded+194@@ -0,0 +1,194 @@+{+ "slug": "sn74als74adr",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Flip Flops, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "logic",+ "sn74als74adr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "sn74als74adr.kicad_sym",+ "sn74als74adr.kicad_mod",+ "sn74als74adr.glb",+ "sn74als74adr.step",+ "sn74als74adr.lbr",+ "docs/hero.png",+ "docs/sn74als74adr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "SN74ALS74ADR",+ "manufacturer": "Texas Instruments",+ "package": "SOIC-14",+ "pin_count": 14,+ "category": "Logic",+ "subcategory": "Flip Flops",+ "datasheet": "https://www.ti.com/lit/ds/symlink/sn74als74a.pdf",+ "parts": {+ "symbol": "sn74als74adr.kicad_sym",+ "footprint": "sn74als74adr.kicad_mod",+ "model_3d": "sn74als74adr-etched.glb",+ "model_3d_plain": "sn74als74adr.glb",+ "model_3d_step": "sn74als74adr-etched.step",+ "model_3d_step_plain": "sn74als74adr.step",+ "lbr": "sn74als74adr.lbr"+ },+ "distributor_links": {+ "lcsc": "C2677819",+ "digikey": "296-1130-2-ND",+ "mouser": "595-SN74ALS74ADR"+ },+ "distributor_check": {+ "checked_at": "2026-09-30T01:40:18Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-1130-2-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-SN74ALS74ADR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "1CLR",+ "type": "input",+ "description": "Flip-flop 1 clear input; a low level resets the outputs regardless of the other inputs."+ },+ {+ "number": "2",+ "name": "1D",+ "type": "input",+ "description": "Flip-flop 1 data input; transferred to the outputs on the positive-going clock edge when PRE and CLR are high."+ },+ {+ "number": "3",+ "name": "1CLK",+ "type": "input",+ "description": "Flip-flop 1 clock input, positive-edge triggered at a voltage level and not directly related to the rise time."+ },+ {+ "number": "4",+ "name": "1PRE",+ "type": "input",+ "description": "Flip-flop 1 preset input; a low level sets the outputs regardless of the other inputs."+ },+ {+ "number": "5",+ "name": "1Q",+ "type": "output",+ "description": "Flip-flop 1 true output."+ },+ {+ "number": "6",+ "name": "1Q̅",+ "type": "output",+ "description": "Flip-flop 1 complementary output."+ },+ {+ "number": "7",+ "name": "GND",+ "type": "power_in",+ "description": "Ground."+ },+ {+ "number": "8",+ "name": "2Q̅",+ "type": "output",+ "description": "Flip-flop 2 complementary output."+ },+ {+ "number": "9",+ "name": "2Q",+ "type": "output",+ "description": "Flip-flop 2 true output."+ },+ {+ "number": "10",+ "name": "2PRE",+ "type": "input",+ "description": "Flip-flop 2 preset input; a low level sets the outputs regardless of the other inputs."+ },+ {+ "number": "11",+ "name": "2CLK",+ "type": "input",+ "description": "Flip-flop 2 clock input, positive-edge triggered at a voltage level and not directly related to the rise time."+ },+ {+ "number": "12",+ "name": "2D",+ "type": "input",+ "description": "Flip-flop 2 data input; transferred to the outputs on the positive-going clock edge when PRE and CLR are high."+ },+ {+ "number": "13",+ "name": "2CLR",+ "type": "input",+ "description": "Flip-flop 2 clear input; a low level resets the outputs regardless of the other inputs."+ },+ {+ "number": "14",+ "name": "VCC",+ "type": "power_in",+ "description": "Supply voltage, 4.5 V to 5.5 V recommended (7 V absolute maximum)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "1/14 pin names appear NOWHERE in the datasheet text: ['9:2Q_N@p1']"+ ],+ "pages_sent": 23,+ "cost_usd": 0.1757,+ "at": "2026-09-30T01:40:03"+ },+ "datasheet": {+ "url": "https://www.ti.com/lit/ds/symlink/sn74als74a.pdf",+ "pages": 23,+ "sha256": "3b44b22e26026ae1",+ "source_tier": "mfr"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 14,+ "described": 14,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}