component

SN74ALS574BDWR

Public Made by Adom

by adom

Texas Instruments Flip Flops, SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogicsn74als574bdwrfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 12d ago
viewers sn74als574bdwr: viewers · Ray 12d ago
package.json Publish 0.1.0 · Ray 12d ago
page.json Set visibility: public · Ray 12d ago
README.md Publish 0.1.0 · Ray 12d ago
sn74als574bdwr-etched.glb sn74als574bdwr: factory component page (tier=lcsc) · Ray 12d ago
sn74als574bdwr-etched.step sn74als574bdwr: factory component page (tier=lcsc) · Ray 12d ago
sn74als574bdwr-hero.glb sn74als574bdwr: hero GLB from the etched model (keeps the MPN mark) · Ray 12d ago
sn74als574bdwr-hero.overlay.json Publish 0.1.0 · Ray 12d ago
sn74als574bdwr.glb Publish 0.1.0 · Ray 12d ago
sn74als574bdwr.kicad_mod Publish 0.1.0 · Ray 12d ago
sn74als574bdwr.kicad_sym Publish 0.1.0 · Ray 12d ago
sn74als574bdwr.lbr Publish 0.1.0 · Ray 12d ago
sn74als574bdwr.step Publish 0.1.0 · Ray 12d ago

SN74ALS574BDWR

Texas Instruments · Flip Flops · SOIC-20-300mil

SN74ALS574BDWR from Texas Instruments, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE input Active-low output enable; when high the 3-state outputs are placed in the high-impedance state, and OE does not affect internal flip-flop operation.
2 1D input Data input to flip-flop 1, entered on the low-to-high transition of CLK with a setup time of 15 ns before CLK↑.
3 2D input Data input to flip-flop 2, entered on the low-to-high transition of CLK with a setup time of 15 ns before CLK↑.
4 3D input Data input to flip-flop 3, entered on the low-to-high transition of CLK with a setup time of 15 ns before CLK↑.
5 4D input Data input to flip-flop 4, entered on the low-to-high transition of CLK with a setup time of 15 ns before CLK↑.
6 5D input Data input to flip-flop 5, entered on the low-to-high transition of CLK with a setup time of 15 ns before CLK↑.
7 6D input Data input to flip-flop 6, entered on the low-to-high transition of CLK with a setup time of 15 ns before CLK↑.
8 7D input Data input to flip-flop 7, entered on the low-to-high transition of CLK with a setup time of 15 ns before CLK↑.
9 8D input Data input to flip-flop 8, entered on the low-to-high transition of CLK with a setup time of 15 ns before CLK↑.
10 GND power_in Ground reference for the device.
11 CLK input Clock input; the eight flip-flops enter data on its low-to-high transition, with a minimum clock pulse width of 16.5 ns high or low per the recommended operating conditions.
12 8Q tri_state Noninverting 3-state output of flip-flop 8 designed to drive bus lines directly, in the high-impedance state when OE is high.
13 7Q tri_state Noninverting 3-state output of flip-flop 7 designed to drive bus lines directly, in the high-impedance state when OE is high.
14 6Q tri_state Noninverting 3-state output of flip-flop 6 designed to drive bus lines directly, in the high-impedance state when OE is high.
15 5Q tri_state Noninverting 3-state output of flip-flop 5 designed to drive bus lines directly, in the high-impedance state when OE is high.
16 4Q tri_state Noninverting 3-state output of flip-flop 4 designed to drive bus lines directly, in the high-impedance state when OE is high.
17 3Q tri_state Noninverting 3-state output of flip-flop 3 designed to drive bus lines directly, in the high-impedance state when OE is high.
18 2Q tri_state Noninverting 3-state output of flip-flop 2 designed to drive bus lines directly, in the high-impedance state when OE is high.
19 1Q tri_state Noninverting 3-state output of flip-flop 1 designed to drive bus lines directly, in the high-impedance state when OE is high.
20 VCC power_in Positive supply; recommended supply voltage is 4.5 V to 5.5 V (nominal 5 V).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-20-300mil
Category Logic
Pins 20

CAD (KiCad official)

  • Symbol: SN74ALS574BDWR
  • Footprint: Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm
  • 3D model: SOIC-20-300mil (KiCad packages3D, STEP)
  • 3D model files: sn74als574bdwr-etched.step / sn74als574bdwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74als574bdwr.step / sn74als574bdwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (23 pp, sha256 481b7b6fa6c6803b, retrieved 2026-10-10, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF