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SN74ALS165DR

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Texas Instruments Logic ICs, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN74ALS165DR

Texas Instruments · Logic ICs · SOIC-16

SN74ALS165DR from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SH/LD input Shift/load control: a low level enables parallel loading of data inputs A through H, and a high level permits clocking, per the function table.
2 CLK input Clock input: a low-to-high transition shifts the register when SH/LD is high and CLK INH is low.
3 E input Parallel data input E, loaded into its register stage while SH/LD is low, independent of the CLK, CLK INH and SER levels.
4 F input Parallel data input F, loaded into its register stage while SH/LD is low, independent of the CLK, CLK INH and SER levels.
5 G input Parallel data input G, loaded into its register stage while SH/LD is low, independent of the CLK, CLK INH and SER levels.
6 H input Parallel data input H, loaded into its register stage while SH/LD is low, independent of the CLK, CLK INH and SER levels.
7 QH̄ output Complementary serial output of the last register stage, the inverse of QH.
8 GND power_in Ground reference for the device.
9 QH output Serial output of the last register stage.
10 SER input Serial data input, shifted into the first register stage on each shift clock.
11 A input Parallel data input A, loaded into its register stage while SH/LD is low.
12 B input Parallel data input B, loaded into its register stage while SH/LD is low.
13 C input Parallel data input C, loaded into its register stage while SH/LD is low.
14 D input Parallel data input D, loaded into its register stage while SH/LD is low.
15 CLK INH input Clock inhibit input: CLK INH should be changed to the high level only while CLK is high, since CLK and CLK INH are interchangeable clock inputs.
16 VCC power_in Supply voltage, recommended 4.5 V to 5.5 V (nominal 5 V) per the recommended operating conditions.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16
Category Logic ICs
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 4.5 5 5.5 V 4
High-level input voltage VIH 2 V 4
Low-level input voltage VIL 0.8 V 4
High-level output current IOH -0.4 mA 4
Low-level output current IOL 8 mA 4
Clock frequency fclock 0 45 MHz 4
Pulse duration, CLK high tw(CLK) 11 ns CLK high, see Figure 1 4
Pulse duration, CLK low tw(CLK) 11 ns CLK low, see Figure 1 4
Pulse duration, SH/LD low tw(load) 12 ns CLK low 4
Setup time, clock enable tsu1 11 ns see Figure 1 4
Setup time, parallel input tsu2 10 ns see Figure 1 4
Setup time, serial input tsu3 10 ns see Figure 2 4
Setup time, shift tsu4 10 ns see Figure 2 4
Hold time at any input th 4 ns 4
Operating free-air temperature TA 0 70 °C 4
Input clamp voltage VIK -1.5 V VCC = 4.5 V, II = −18 mA 4
Low-level output voltage VOL 0.25 0.4 V VCC = 4.5 V, IOL = 4 mA 4
Low-level output voltage VOL 0.35 0.5 V VCC = 4.5 V, IOL = 8 mA 4
Input current at maximum input voltage II 0.1 mA VCC = 5.5 V, VI = 7 V 4
High-level input current IIH 20 µA VCC = 5.5 V, VI = 2.7 V 4
Low-level input current IIL -0.1 mA VCC = 5.5 V, VI = 0.4 V 4
Output current IO -30 -112 mA VCC = 5.5 V, VO = 2.25 V 4
Supply current ICC 12 24 mA VCC = 5.5 V, see Note 1 4
Maximum clock frequency fmax 45 MHz VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX 5
Propagation delay, low-to-high output, SH/LD to any output tPLH 4 20 ns VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX 5
Propagation delay, high-to-low output, SH/LD to any output tPHL 4 22 ns VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX 5
Propagation delay, low-to-high output, CLK to any output tPLH 3 13 ns VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX 5
Propagation delay, high-to-low output, CLK to any output tPHL 3 14 ns VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX 5
Propagation delay, low-to-high output, H to QH (first row) tPLH 3 13 ns VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX 5
Propagation delay, high-to-low output, H to QH (first row) tPHL 3 16 ns VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX 5
Propagation delay, low-to-high output, H to QH (second row) tPLH 2 15 ns VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX 5
Propagation delay, high-to-low output, H to QH (second row) tPHL 3 16 ns VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX 5
Supply voltage VCC 7 V 3
Input voltage VI 7 V 3
Operating free-air temperature range (SN74ALS165) TA 0 70 °C 3
Storage temperature range Tstg -65 150 °C 3

CAD (KiCad official)

  • Symbol: SN74ALS165DR
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: sn74als165dr-etched.step / sn74als165dr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74als165dr.step / sn74als165dr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (13 pp, sha256 d98b72e3fd37aca1, retrieved 2026-10-18, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF