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SN74ALS164ADR

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Texas Instruments Shift Registers, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN74ALS164ADR

Texas Instruments · Shift Registers · SOIC-14

SN74ALS164ADR from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A input AND-gated serial data input: a low at A inhibits entry of new data and resets the first flip-flop to low at the next clock pulse, and A determines the first flip-flop state only while B is high.
2 B input AND-gated serial data input: a low at B inhibits entry of new data and resets the first flip-flop to low at the next clock pulse, and B determines the first flip-flop state only while A is high.
3 QA output Parallel output of the first register stage, which takes the AND of the serial inputs on each low-to-high CLK transition and is forced low by CLR.
4 QB output Parallel output of register stage B, which shifts in the previous QA level on each low-to-high CLK transition and is forced low by CLR.
5 QC output Parallel output of register stage C, which shifts in the previous QB level on each low-to-high CLK transition and is forced low by CLR.
6 QD output Parallel output of register stage D, which shifts in the previous QC level on each low-to-high CLK transition and is forced low by CLR.
7 GND power_in Ground reference for the device.
8 CLK input Clock input; data shifts on the low-to-high-level transition of CLK and the clock input is fully buffered.
9 CLR input Direct asynchronous clear: a low level sets all outputs QA through QH to low regardless of the clock.
10 QE output Parallel output of register stage E, which shifts in the previous QD level on each low-to-high CLK transition and is forced low by CLR.
11 QF output Parallel output of register stage F, which shifts in the previous QE level on each low-to-high CLK transition and is forced low by CLR.
12 QG output Parallel output of register stage G, which shifts in the previous QF level on each low-to-high CLK transition and is forced low by CLR.
13 QH output Parallel output of the last register stage H, which shifts in the previous QG level on each low-to-high CLK transition and is forced low by CLR.
14 VCC power_in Supply voltage: recommended 4.5 V to 5.5 V (5 V nominal), with an absolute maximum of 7 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-14
Category Logic
Pins 14

CAD (KiCad official)

  • Symbol: SN74ALS164ADR
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOIC-14 (KiCad packages3D, STEP)
  • 3D model files: sn74als164adr-etched.step / sn74als164adr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74als164adr.step / sn74als164adr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (16 pp, sha256 4624bf87e3523224, retrieved 2026-10-11, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF