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SN74AHCT595N

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Texas Instruments Shifting Register, PDIP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN74AHCT595N

Texas Instruments · Shifting Register · PDIP-16

SN74AHCT595N from Texas Instruments, in a PDIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 QB tri_state QB 3-state storage-register output, high-impedance when OE is high.
2 QC tri_state QC 3-state storage-register output, high-impedance when OE is high.
3 QD tri_state QD 3-state storage-register output, high-impedance when OE is high.
4 QE tri_state QE 3-state storage-register output, high-impedance when OE is high.
5 QF tri_state QF 3-state storage-register output, high-impedance when OE is high.
6 QG tri_state QG 3-state storage-register output, high-impedance when OE is high.
7 QH tri_state QH 3-state storage-register output, high-impedance when OE is high.
8 GND power_in Ground pin.
9 QH' output Serial output of the shift register for cascading, not 3-state.
10 SRCLR input Active-low direct clear of the shift register (shift register is cleared when low).
11 SRCLK input Shift register clock input, positive-edge triggered.
12 RCLK input Storage register clock input, positive-edge triggered; stores shift-register data.
13 OE input Output enable; outputs QA-QH are in the high-impedance state when high and enabled when low.
14 SER input Serial data input to the shift register.
15 QA tri_state QA 3-state storage-register output, high-impedance when OE is high.
16 VCC power_in Power supply pin, 4.5 V to 5.5 V recommended operating range.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package PDIP-16
Category Logic ICs
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 4.5 5.5 V 4
High-level input voltage VIH 2 V 4
Low-level input voltage VIL 0.8 V 4
Input voltage VI 0 5.5 V 4
Output voltage VO 0 V max = VCC 4
High-level output current IOH -8 mA 4
Low-level output current IOL 8 mA 4
Input transition rise and fall time Δt/Δv 20 ns/V 4
Operating free-air temperature TA -40 125 °C 4
Supply voltage range VCC -0.5 7 V 4
Input voltage range VI -0.5 7 V 4
Output voltage range VO -0.5 V max = VCC + 0.5 V 4
Input clamp current IIK -20 mA VI < 0 4
Output clamp current IOK -20 20 mA VO < 0 or VO > VCC 4
Continuous output current IO -25 25 mA VO = 0 to VCC 4
Continuous current through VCC or GND -50 50 mA 4
Storage temperature range Tstg -65 150 °C 4
ESD HBM V(ESD) 0 2000 V HBM, all pins 4
ESD CDM V(ESD) 0 1000 V CDM, all pins 4
Junction-to-ambient thermal resistance (N) RθJA 47.5 °C/W N package, 16 pins 5
Junction-to-case (top) thermal resistance (N) RθJC(top) 34.9 °C/W N package 5
Junction-to-board thermal resistance (N) RθJB 27.5 °C/W N package 5
Junction-to-top characterization parameter (N) ψJT 19.8 °C/W N package 5
Junction-to-board characterization parameter (N) ψJB 27.4 °C/W N package 5
High-level output voltage VOH 4.4 V IOH = -50 µA, VCC = 4.5 V 5
High-level output voltage VOH 3.8 V IOH = -8 mA, VCC = 4.5 V 5
Low-level output voltage VOL 0.1 V IOL = 50 µA, VCC = 4.5 V 5
Low-level output voltage VOL 0.44 V IOL = 8 mA, VCC = 4.5 V 5
Input leakage current II -1 1 µA VI = 5.5 V or GND, VCC = 0 to 5.5 V 5
Off-state output current IOZ -2.5 2.5 µA VO = VCC or GND, QA, QH, VCC = 5.5 V 5
Supply current ICC 40 µA VI = VCC or GND, IO = 0, VCC = 5.5 V 5
Change in supply current ΔICC 2.2 mA One input at 3.4 V, other inputs at VCC or GND, VCC = 5.5 V 5
Input capacitance Ci 10 pF VI = VCC or GND, VCC = 5 V 5
Output capacitance Co 5.5 pF VO = VCC or GND, VCC = 5 V 5
Pulse duration SRCLK high or low tw 5.5 ns VCC = 5 V ± 0.5 V 5
Pulse duration RCLK high or low tw 5.5 ns VCC = 5 V ± 0.5 V 5
Pulse duration SRCLR low tw 5 ns VCC = 5 V ± 0.5 V 5
Setup time SER before SRCLK↑ tsu 3 ns VCC = 5 V ± 0.5 V 5
Setup time SRCLK↑ before RCLK↑ tsu 5 ns VCC = 5 V ± 0.5 V 5
Setup time SRCLR low before RCLK↑ tsu 5 ns VCC = 5 V ± 0.5 V 5
Setup time SRCLR high (inactive) before SRCLK↑ tsu 3.8 ns VCC = 5 V ± 0.5 V 5
Hold time SER after SRCLK↑ th 2 ns VCC = 5 V ± 0.5 V 5
Maximum clock frequency fmax 115 MHz CL = 15 pF, VCC = 5 V ± 0.5 V 6
Maximum clock frequency fmax 85 MHz CL = 50 pF, VCC = 5 V ± 0.5 V 6
Propagation delay RCLK to QA-QH (tPLH/tPHL) tPLH, tPHL 1 8.5 ns CL = 15 pF 6
Propagation delay SRCLK to QH′ (tPLH/tPHL) tPLH, tPHL 1 9.4 ns CL = 15 pF 6
Propagation delay SRCLR to QH′ tPHL 1 9.1 ns CL = 15 pF 6
Enable time OE to QA-QH (tPZH/tPZL) tPZH, tPZL 1 10 ns CL = 15 pF 6
Propagation delay RCLK to QA-QH (tPLH/tPHL) tPLH, tPHL 1 10.5 ns CL = 50 pF 6
Propagation delay SRCLK to QH′ (tPLH/tPHL) tPLH, tPHL 1 11.4 ns CL = 50 pF 6
Propagation delay SRCLR to QH′ tPHL 1 11.1 ns CL = 50 pF 6
Enable time OE to QA-QH (tPZH/tPZL) tPZH, tPZL 1 12 ns CL = 50 pF 6
Disable time OE to QA-QH (tPHZ/tPLZ) tPHZ, tPLZ 1 11 ns CL = 50 pF 6
Power dissipation capacitance Cpd 112 pF No load, f = 1 MHz, VCC = 5 V, TA = 25°C 7

CAD (KiCad official)

  • Symbol: SN74AHCT595N
  • Footprint: Package_DIP:DIP-16_W7.62mm
  • 3D model: PDIP-16 (KiCad packages3D, STEP)
  • 3D model files: sn74ahct595n-etched.step / sn74ahct595n-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74ahct595n.step / sn74ahct595n.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (28 pp, sha256 0f8b895e2840ffc2, retrieved 2026-10-23, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF