# SN74AHCT594PWR

**Texas Instruments** · Shift Registers · TSSOP-16

SN74AHCT594PWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | QB | output | Parallel output B of the 8-bit storage register; continuous output current must not exceed ±25 mA (absolute maximum, VO = 0 to VCC). |
| 2 | QC | output | Parallel output C of the 8-bit storage register; continuous output current must not exceed ±25 mA (absolute maximum, VO = 0 to VCC). |
| 3 | QD | output | Parallel output D of the 8-bit storage register; continuous output current must not exceed ±25 mA (absolute maximum, VO = 0 to VCC). |
| 4 | QE | output | Parallel output E of the 8-bit storage register; continuous output current must not exceed ±25 mA (absolute maximum, VO = 0 to VCC). |
| 5 | QF | output | Parallel output F of the 8-bit storage register; continuous output current must not exceed ±25 mA (absolute maximum, VO = 0 to VCC). |
| 6 | QG | output | Parallel output G of the 8-bit storage register; continuous output current must not exceed ±25 mA (absolute maximum, VO = 0 to VCC). |
| 7 | QH | output | Parallel output H of the 8-bit storage register; continuous output current must not exceed ±25 mA (absolute maximum, VO = 0 to VCC). |
| 8 | GND | power_in | Ground pin, the device reference potential. |
| 9 | QH' | output | Serial output QH' (inverted QH) provided for cascading purposes to a following device. |
| 10 | SRCLR | input | Active-low serial (shift register) clear; when low it clears the shift register independently of the clock. |
| 11 | SRCLK | input | Shift register clock, positive-edge triggered; SER is shifted in on the rising edge, with SER setup of 3 ns and hold of 2 ns minimum at 25°C. |
| 12 | RCLK | input | Storage register clock, positive-edge triggered; shift register data is transferred to the storage register on the rising edge. |
| 13 | RCLR | input | Active-low storage register clear; when low it clears the storage register independently of the clock. |
| 14 | SER | input | Serial data input to the shift register, sampled on the rising edge of SRCLK; VIH 2 V and VIL 0.8 V with 5.5 V input tolerance. |
| 15 | QA | output | Parallel output A of the 8-bit storage register; continuous output current must not exceed ±25 mA (absolute maximum, VO = 0 to VCC). |
| 16 | VCC | power_in | Supply pin; recommended supply range 4.5 V to 5.5 V, with VCC optimized at 5 V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-16 |
| Category | Logic |
| Pins | 16 |

## CAD (KiCad official)

- Symbol: `SN74AHCT594PWR`
- Footprint: `Package_SO:TSSOP-16_4.4x5mm_P0.65mm`
- 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files: `sn74ahct594pwr-etched.step` / `sn74ahct594pwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74ahct594pwr.step` / `sn74ahct594pwr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/sn74ahct594.pdf) (31 pp, sha256 `fc0a7ee66d7d3d24`, retrieved 2026-10-11, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/sn74ahct594pwr-datasheet.pdf)