component
SN74AHCT594DR
Public Made by Adomby adom
Texas Instruments Shift Registers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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"lcsc": "C2878048",
"digikey": "296-48660-2-ND",
"mouser": "595-SN74AHCT594DR"
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"pins": [
{
"number": "1",
"name": "QB",
"type": "output",
"description": "Output B, a parallel output of the 8-bit storage register; load current should not exceed 25 mA per output (Section 8.2.2)."
},
{
"number": "2",
"name": "QC",
"type": "output",
"description": "Output C, a parallel output of the 8-bit storage register; load current should not exceed 25 mA per output (Section 8.2.2)."
},
{
"number": "3",
"name": "QD",
"type": "output",
"description": "Output D, a parallel output of the 8-bit storage register; load current should not exceed 25 mA per output (Section 8.2.2)."
},
{
"number": "4",
"name": "QE",
"type": "output",
"description": "Output E, a parallel output of the 8-bit storage register; load current should not exceed 25 mA per output (Section 8.2.2)."
},
{
"number": "5",
"name": "QF",
"type": "output",
"description": "Output F, a parallel output of the 8-bit storage register; load current should not exceed 25 mA per output (Section 8.2.2)."
},
{
"number": "6",
"name": "QG",
"type": "output",
"description": "Output G, a parallel output of the 8-bit storage register; load current should not exceed 25 mA per output (Section 8.2.2)."
},
{
"number": "7",
"name": "QH",
"type": "output",
"description": "Output H, a parallel output of the 8-bit storage register; load current should not exceed 25 mA per output (Section 8.2.2)."
},
{
"number": "8",
"name": "GND",
"type": "power_in",
"description": "Ground pin."
},
{
"number": "9",
"name": "QH'",
"type": "output",
"description": "Serial output QH' (QH inverted) provided for cascading multiple devices; load current should not exceed 25 mA per output (Section 8.2.2)."
},
{
"number": "10",
"name": "SRCLR",
"type": "input",
"description": "Serial (shift register) clear input; when low it clears the shift register independently of the other inputs (Function Table, Section 7.4)."
},
{
"number": "11",
"name": "SRCLK",
"type": "input",
"description": "Shift register clock; positive-edge triggered, with the shift register one count ahead of the storage register when both clocks are tied together (Section 7.1)."
},
{
"number": "12",
"name": "RCLK",
"type": "input",
"description": "Storage register clock; positive-edge triggered, transferring shift register data into the storage register (Section 7.1 and 7.4)."
},
{
"number": "13",
"name": "RCLR",
"type": "input",
"description": "Storage register clear input; when low it clears the storage register independently of the shift register (Function Table, Section 7.4)."
},
{
"number": "14",
"name": "SER",
"type": "input",
"description": "Serial data input to the 8-bit shift register; sampled on the SRCLK rising edge (Function Table, Section 7.4)."
},
{
"number": "15",
"name": "QA",
"type": "output",
"description": "Output A, a parallel output of the 8-bit storage register; load current should not exceed 25 mA per output (Section 8.2.2)."
},
{
"number": "16",
"name": "VCC",
"type": "power_in",
"description": "Power supply pin; recommended supply range is 4.5 V to 5.5 V (Section 5.3)."
}
],
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"guards": "pin_guards 0.1: passed",
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"extractor flagged: The TI pin table lists QH' as type 'I' (input), but the datasheet describes QH' as the serial output; The TI pin table gives GND as '—' and VCC as 'Power pin' with no direction. Typed as power_in per th; The pin table in Section 4 is a single table covering all 16-pin package variants (D, DB, N, NS, PW)"
],
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"Package": "SOIC-16",
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