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SN74AHCT573PWR

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Texas Instruments Latches, TSSOP-20. Datasheet-verified pinout, KiCad symbol/footprint/3D.

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Contents

README

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SN74AHCT573PWR

Texas Instruments · Latches · TSSOP-20

SN74AHCT573PWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE input Output Enable (active-low); when low enables normal Q output drive, when high places all eight outputs in high-impedance state.
2 1D input Data input 1 for transparent D-latch; TTL-compatible threshold 0.8V (low) to 2V (high).
3 2D input Data input 2 for transparent D-latch; TTL-compatible threshold 0.8V (low) to 2V (high).
4 3D input Data input 3 for transparent D-latch; TTL-compatible threshold 0.8V (low) to 2V (high).
5 4D input Data input 4 for transparent D-latch; TTL-compatible threshold 0.8V (low) to 2V (high).
6 5D input Data input 5 for transparent D-latch; TTL-compatible threshold 0.8V (low) to 2V (high).
7 6D input Data input 6 for transparent D-latch; TTL-compatible threshold 0.8V (low) to 2V (high).
8 7D input Data input 7 for transparent D-latch; TTL-compatible threshold 0.8V (low) to 2V (high).
9 8D input Data input 8 for transparent D-latch; TTL-compatible threshold 0.8V (low) to 2V (high).
10 GND power_in Ground (0V reference).
11 LE input Latch Enable (active-high); when high Q outputs follow D inputs transparently, when low Q outputs latch; minimum pulse width 5ns.
12 8Q tri_state Q8 tri-state output; follows D8 when LE high, latches when LE low, high-impedance when OE high; ±25mA per pin, ±75mA total device.
13 7Q tri_state Q7 tri-state output; follows D7 when LE high, latches when LE low, high-impedance when OE high; ±25mA per pin, ±75mA total device.
14 6Q tri_state Q6 tri-state output; follows D6 when LE high, latches when LE low, high-impedance when OE high; ±25mA per pin, ±75mA total device.
15 5Q tri_state Q5 tri-state output; follows D5 when LE high, latches when LE low, high-impedance when OE high; ±25mA per pin, ±75mA total device.
16 4Q tri_state Q4 tri-state output; follows D4 when LE high, latches when LE low, high-impedance when OE high; ±25mA per pin, ±75mA total device.
17 3Q tri_state Q3 tri-state output; follows D3 when LE high, latches when LE low, high-impedance when OE high; ±25mA per pin, ±75mA total device.
18 2Q tri_state Q2 tri-state output; follows D2 when LE high, latches when LE low, high-impedance when OE high; ±25mA per pin, ±75mA total device.
19 1Q tri_state Q1 tri-state output; follows D1 when LE high, latches when LE low, high-impedance when OE high; ±25mA per pin, ±75mA total device.
20 VCC power_in Power supply; 4.5V to 5.5V recommended operating range.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-20
Category Logic
Pins 20

CAD (KiCad official)

  • Symbol: SN74AHCT573PWR
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: sn74ahct573pwr-etched.step / sn74ahct573pwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74ahct573pwr.step / sn74ahct573pwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (39 pp, sha256 2067a88a3f9abb5c, retrieved 2026-09-22, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF