component
SN74AHCT367DR
Public Made by Adomby adom
Texas Instruments Buffers, Drivers, Receivers, Transceivers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSN74AHCT367DR
Texas Instruments · Buffers, Drivers, Receivers, Transceivers · SOIC-16
SN74AHCT367DR from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1OE | input | Active-low output enable input for channel 1 (4 buffers); when low outputs pass input data, when high outputs are high-impedance |
| 2 | 1A1 | input | Channel 1 buffer 1 input; accepts TTL-compatible input levels 0 V to 5.5 V |
| 3 | 1Y1 | tri_state | Channel 1 buffer 1 3-state output; active when 1OE is low, high-impedance when 1OE is high |
| 4 | 1A2 | input | Channel 1 buffer 2 input; accepts TTL-compatible input levels 0 V to 5.5 V |
| 5 | 1Y2 | tri_state | Channel 1 buffer 2 3-state output; active when 1OE is low, high-impedance when 1OE is high |
| 6 | 1A3 | input | Channel 1 buffer 3 input; accepts TTL-compatible input levels 0 V to 5.5 V |
| 7 | 1Y3 | tri_state | Channel 1 buffer 3 3-state output; active when 1OE is low, high-impedance when 1OE is high |
| 8 | GND | power_in | Ground reference pin (0 V) |
| 9 | 1Y4 | tri_state | Channel 1 buffer 4 3-state output; active when 1OE is low, high-impedance when 1OE is high |
| 10 | 1A4 | input | Channel 1 buffer 4 input; accepts TTL-compatible input levels 0 V to 5.5 V |
| 11 | 2Y1 | tri_state | Channel 2 buffer 1 3-state output; active when 2OE is low, high-impedance when 2OE is high |
| 12 | 2A1 | input | Channel 2 buffer 1 input; accepts TTL-compatible input levels 0 V to 5.5 V |
| 13 | 2Y2 | tri_state | Channel 2 buffer 2 3-state output; active when 2OE is low, high-impedance when 2OE is high |
| 14 | 2A2 | input | Channel 2 buffer 2 input; accepts TTL-compatible input levels 0 V to 5.5 V |
| 15 | 2OE | input | Active-low output enable input for channel 2 (2 buffers); when low outputs pass input data, when high outputs are high-impedance |
| 16 | VCC | power_in | Power supply input pin; recommended operating range 4.5 V to 5.5 V |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-16 |
| Category | Logic |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
SN74AHCT367DR - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files:
sn74ahct367dr-etched.step/sn74ahct367dr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74ahct367dr.step/sn74ahct367dr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (26 pp, sha256
b159c5e2bc0885ea, retrieved 2026-09-22, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).