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SN74AHCT32QPWRG4Q1

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Texas Instruments Logic Gates, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN74AHCT32QPWRG4Q1

Texas Instruments · Logic Gates · TSSOP-14

SN74AHCT32QPWRG4Q1 from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Logic input of gate 1; inputs must stay within 0 V to 5.5 V and unused inputs must be tied to VCC or GND, not left floating.
2 1B input Logic input of gate 1; inputs must stay within 0 V to 5.5 V and unused inputs must be tied to VCC or GND, not left floating.
3 1Y output Logic output of gate 1; rated for ±8 mA at 5 V (IOH = -8 mA, IOL = 8 mA), and an unused output may be left floating.
4 2A input Logic input of gate 2; inputs must stay within 0 V to 5.5 V and unused inputs must be tied to VCC or GND, not left floating.
5 2B input Logic input of gate 2; inputs must stay within 0 V to 5.5 V and unused inputs must be tied to VCC or GND, not left floating.
6 2Y output Logic output of gate 2; rated for ±8 mA at 5 V (IOH = -8 mA, IOL = 8 mA), and an unused output may be left floating.
7 GND power_in Ground pin; must be able to sink the total output current plus the maximum supply current ICC and any transient current, and current through GND must not exceed the ±50 mA absolute maximum.
8 3Y output Logic output of gate 3; rated for ±8 mA at 5 V (IOH = -8 mA, IOL = 8 mA), and an unused output may be left floating.
9 3A input Logic input of gate 3; inputs must stay within 0 V to 5.5 V and unused inputs must be tied to VCC or GND, not left floating.
10 3B input Logic input of gate 3; inputs must stay within 0 V to 5.5 V and unused inputs must be tied to VCC or GND, not left floating.
11 4Y output Logic output of gate 4; rated for ±8 mA at 5 V (IOH = -8 mA, IOL = 8 mA), and an unused output may be left floating.
12 4A input Logic input of gate 4; inputs must stay within 0 V to 5.5 V and unused inputs must be tied to VCC or GND, not left floating.
13 4B input Logic input of gate 4; inputs must stay within 0 V to 5.5 V and unused inputs must be tied to VCC or GND, not left floating.
14 VCC power_in Supply pin; operating range is 4.5 V to 5.5 V, with a 0.1 µF bypass capacitor placed close to the device recommended.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-14
Category Logic
Pins 14

CAD (KiCad official)

  • Symbol: SN74AHCT32QPWRG4Q1
  • Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
  • 3D model: TSSOP-14 (KiCad packages3D, STEP)
  • 3D model files: sn74ahct32qpwrg4q1-etched.step / sn74ahct32qpwrg4q1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74ahct32qpwrg4q1.step / sn74ahct32qpwrg4q1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (28 pp, sha256 754593b083eb624c, retrieved 2026-10-10, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF