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SN74AHCT244QPWRQ1

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Texas Instruments Buffers / Drivers, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN74AHCT244QPWRQ1

Texas Instruments · Buffers / Drivers · TSSOP-20

SN74AHCT244QPWRQ1 from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1OE input Output enable for the 1Y outputs, active low; when high the 1Y outputs are high-impedance.
2 1A1 input Channel 1 data input of the first 4-bit buffer, TTL-compatible, passed to 1Y1 when 1OE is low.
3 2Y4 tri_state Channel 4 3-state output of the second 4-bit buffer, follows 2A4 when 2OE is low and is high-impedance when 2OE is high.
4 1A2 input Channel 2 data input of the first 4-bit buffer, TTL-compatible, passed to 1Y2 when 1OE is low.
5 2Y3 tri_state Channel 3 3-state output of the second 4-bit buffer, follows 2A3 when 2OE is low and is high-impedance when 2OE is high.
6 1A3 input Channel 3 data input of the first 4-bit buffer, TTL-compatible, passed to 1Y3 when 1OE is low.
7 2Y2 tri_state Channel 2 3-state output of the second 4-bit buffer, follows 2A2 when 2OE is low and is high-impedance when 2OE is high.
8 1A4 input Channel 4 data input of the first 4-bit buffer, TTL-compatible, passed to 1Y4 when 1OE is low.
9 2Y1 tri_state Channel 1 3-state output of the second 4-bit buffer, follows 2A1 when 2OE is low and is high-impedance when 2OE is high.
10 GND power_in Ground pin.
11 2A1 input Channel 1 data input of the second 4-bit buffer, TTL-compatible, passed to 2Y1 when 2OE is low.
12 1Y4 tri_state Channel 4 3-state output of the first 4-bit buffer, follows 1A4 when 1OE is low and is high-impedance when 1OE is high.
13 2A2 input Channel 2 data input of the second 4-bit buffer, TTL-compatible, passed to 2Y2 when 2OE is low.
14 1Y3 tri_state Channel 3 3-state output of the first 4-bit buffer, follows 1A3 when 1OE is low and is high-impedance when 1OE is high.
15 2A3 input Channel 3 data input of the second 4-bit buffer, TTL-compatible, passed to 2Y3 when 2OE is low.
16 1Y2 tri_state Channel 2 3-state output of the first 4-bit buffer, follows 1A2 when 1OE is low and is high-impedance when 1OE is high.
17 2A4 input Channel 4 data input of the second 4-bit buffer, TTL-compatible, passed to 2Y4 when 2OE is low.
18 1Y1 tri_state Channel 1 3-state output of the first 4-bit buffer, follows 1A1 when 1OE is low and is high-impedance when 1OE is high.
19 2OE input Output enable for the 2Y outputs, active low; when high the 2Y outputs are high-impedance.
20 VCC power_in Supply voltage, recommended 4.5 V to 5.5 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-20
Category Logic ICs
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 4.5 5.5 V 2
High-level input voltage VIH 2 V 2
Low-level input voltage VIL 0.8 V 2
Input voltage VI 0 5.5 V 2
Output voltage VO 0 V max is VCC 2
High-level output current IOH -8 mA 2
Low-level output current IOL 8 mA 2
Operating free-air temperature, Q-suffix TA -40 125 °C Q-suffix device 2
Supply voltage range VCC -0.5 7 V 2
Input voltage range VI -0.5 7 V see Note 1 2
Output voltage range VO -0.5 5.5 V see Note 1; printed as VCC + 0.5 V (not evaluated) 2
Input clamp current IIK -20 mA VI < 0 2
Output clamp current IOK -20 20 mA VO < 0 or VO > VCC 2
Continuous output current IO -25 25 mA VO = 0 to VCC 2
Continuous current through VCC or GND -75 75 mA 2
Storage temperature range Tstg -65 150 °C 2
Package thermal impedance, PW package θJA 83 °C/W see Note 2, JESD 51-7 2
High-level output voltage VOH 4.4 V IOH = -50 µA, VCC = 4.5 V, full temp range 3
High-level output voltage VOH 3.8 V IOH = -8 mA, VCC = 4.5 V, full temp range 3
Low-level output voltage VOL 0.1 V IOL = 50 µA, VCC = 4.5 V 3
Low-level output voltage VOL 0.44 V IOL = 8 mA, VCC = 4.5 V, full temp range 3
Off-state output current IOZ -2.5 2.5 µA VO = VCC or GND, VCC = 5.5 V, full temp range 3
Input current II -1 1 µA VI = 5.5 V or GND, VCC = 0 V to 5.5 V, full temp range 3
Supply current ICC 40 µA VI = VCC or GND, IO = 0, VCC = 5.5 V, full temp range 3
Supply current change ΔICC 1.5 mA One input at 3.4 V, other inputs at VCC or GND, VCC = 5.5 V, full temp range 3
Input capacitance Ci 2.5 10 pF VI = VCC or GND, VCC = 5 V, TA = 25°C 3
Output capacitance Co 3 pF VO = VCC or GND, VCC = 5 V 3
Propagation delay A to Y (tPLH, tPHL) tPLH/tPHL 1 8.5 ns CL = 15 pF, VCC = 5 V ± 0.5 V, full temp range 3
Enable time OE to Y (tPZH, tPZL) tPZH/tPZL 1 12 ns CL = 15 pF, VCC = 5 V ± 0.5 V, full temp range 3
Disable time OE to Y (tPHZ, tPLZ) tPHZ/tPLZ 1 10 ns CL = 15 pF, VCC = 5 V ± 0.5 V, full temp range 3
Propagation delay A to Y (tPLH, tPHL) tPLH/tPHL 1 9.5 ns CL = 50 pF, VCC = 5 V ± 0.5 V, full temp range 3
Enable time OE to Y (tPZH, tPZL) tPZH/tPZL 1 13 ns CL = 50 pF, VCC = 5 V ± 0.5 V, full temp range 3
Disable time OE to Y (tPHZ, tPLZ) tPHZ/tPLZ 1 13 ns CL = 50 pF, VCC = 5 V ± 0.5 V, full temp range 3
Skew between outputs tsk(o) 1 ns CL = 50 pF 3
Quiet output, minimum dynamic VOH VOH(V) 4.1 V VCC = 5 V, CL = 50 pF, TA = 25°C 3
High-level dynamic input voltage VIH(D) 2 V VCC = 5 V, CL = 50 pF, TA = 25°C 3
Low-level dynamic input voltage VIL(D) 0.8 V VCC = 5 V, CL = 50 pF, TA = 25°C 3
Power dissipation capacitance Cpd 8.2 pF No load, f = 1 MHz, VCC = 5 V, TA = 25°C 3

CAD (KiCad official)

  • Symbol: SN74AHCT244QPWRQ1
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: sn74ahct244qpwrq1-etched.step / sn74ahct244qpwrq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74ahct244qpwrq1.step / sn74ahct244qpwrq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (16 pp, sha256 6a442df7c07e7e39, retrieved 2026-10-27, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF