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SN74AHCT244MPWREP
Public Made by Adomby adom
Texas Instruments Buffers, Drivers, Receivers, Transceivers, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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SN74AHCT244MPWREP
Texas Instruments · Buffers, Drivers, Receivers, Transceivers · TSSOP-20
SN74AHCT244MPWREP from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1OE | input | Active-low output enable for the first 4-bit buffer; when low the 1Y outputs follow the 1A inputs, and when high the 1Y outputs go to the high-impedance state. |
| 2 | 1A1 | input | Data input to the first buffer channel, with an input voltage range of 0 V to 5.5 V, TTL-voltage compatible with VIH minimum 2 V and VIL maximum 0.8 V. |
| 3 | 2Y4 | tri_state | 3-state buffer output of the second bank, high impedance when 2OE is high, with output voltage limited to 0 V to VCC and recommended IOH of -8 mA and IOL of 8 mA. |
| 4 | 1A2 | input | Data input to the first buffer channel, with an input voltage range of 0 V to 5.5 V, TTL-voltage compatible with VIH minimum 2 V and VIL maximum 0.8 V. |
| 5 | 2Y3 | tri_state | 3-state buffer output of the second bank, high impedance when 2OE is high, with output voltage limited to 0 V to VCC and recommended IOH of -8 mA and IOL of 8 mA. |
| 6 | 1A3 | input | Data input to the first buffer channel, with an input voltage range of 0 V to 5.5 V, TTL-voltage compatible with VIH minimum 2 V and VIL maximum 0.8 V. |
| 7 | 2Y2 | tri_state | 3-state buffer output of the second bank, high impedance when 2OE is high, with output voltage limited to 0 V to VCC and recommended IOH of -8 mA and IOL of 8 mA. |
| 8 | 1A4 | input | Data input to the first buffer channel, with an input voltage range of 0 V to 5.5 V, TTL-voltage compatible with VIH minimum 2 V and VIL maximum 0.8 V. |
| 9 | 2Y1 | tri_state | 3-state buffer output of the second bank, high impedance when 2OE is high, with output voltage limited to 0 V to VCC and recommended IOH of -8 mA and IOL of 8 mA. |
| 10 | GND | power_in | Device ground connection. |
| 11 | 2A1 | input | Data input to the second buffer channel, with an input voltage range of 0 V to 5.5 V, TTL-voltage compatible with VIH minimum 2 V and VIL maximum 0.8 V. |
| 12 | 1Y4 | tri_state | 3-state buffer output of the first bank, high impedance when 1OE is high, with output voltage limited to 0 V to VCC and recommended IOH of -8 mA and IOL of 8 mA. |
| 13 | 2A2 | input | Data input to the second buffer channel, with an input voltage range of 0 V to 5.5 V, TTL-voltage compatible with VIH minimum 2 V and VIL maximum 0.8 V. |
| 14 | 1Y3 | tri_state | 3-state buffer output of the first bank, high impedance when 1OE is high, with output voltage limited to 0 V to VCC and recommended IOH of -8 mA and IOL of 8 mA. |
| 15 | 2A3 | input | Data input to the second buffer channel, with an input voltage range of 0 V to 5.5 V, TTL-voltage compatible with VIH minimum 2 V and VIL maximum 0.8 V. |
| 16 | 1Y2 | tri_state | 3-state buffer output of the first bank, high impedance when 1OE is high, with output voltage limited to 0 V to VCC and recommended IOH of -8 mA and IOL of 8 mA. |
| 17 | 2A4 | input | Data input to the second buffer channel, with an input voltage range of 0 V to 5.5 V, TTL-voltage compatible with VIH minimum 2 V and VIL maximum 0.8 V. |
| 18 | 1Y1 | tri_state | 3-state buffer output of the first bank, high impedance when 1OE is high, with output voltage limited to 0 V to VCC and recommended IOH of -8 mA and IOL of 8 mA. |
| 19 | 2OE | input | Active-low output enable for the second 4-bit buffer; when low the 2Y outputs follow the 2A inputs, and when high the 2Y outputs go to the high-impedance state. |
| 20 | VCC | power_in | Supply voltage, recommended range 4.5 V to 5.5 V; tie OE to VCC through a pullup resistor to keep outputs high-impedance during power up or down. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-20 |
| Category | Logic |
| Pins | 20 |
CAD (KiCad official)
- Symbol:
SN74AHCT244MPWREP - Footprint:
Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm - 3D model: TSSOP-20 (KiCad packages3D, STEP)
- 3D model files:
sn74ahct244mpwrep-etched.step/sn74ahct244mpwrep-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74ahct244mpwrep.step/sn74ahct244mpwrep.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (10 pp, sha256
ef24c4b9d7fff0f9, retrieved 2026-10-11, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# SN74AHCT244MPWREP
**Texas Instruments** · Buffers, Drivers, Receivers, Transceivers · TSSOP-20
SN74AHCT244MPWREP from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1OE | input | Active-low output enable for the first 4-bit buffer; when low the 1Y outputs follow the 1A inputs, and when high the 1Y outputs go to the high-impedance state. |
| 2 | 1A1 | input | Data input to the first buffer channel, with an input voltage range of 0 V to 5.5 V, TTL-voltage compatible with VIH minimum 2 V and VIL maximum 0.8 V. |
| 3 | 2Y4 | tri_state | 3-state buffer output of the second bank, high impedance when 2OE is high, with output voltage limited to 0 V to VCC and recommended IOH of -8 mA and IOL of 8 mA. |
| 4 | 1A2 | input | Data input to the first buffer channel, with an input voltage range of 0 V to 5.5 V, TTL-voltage compatible with VIH minimum 2 V and VIL maximum 0.8 V. |
| 5 | 2Y3 | tri_state | 3-state buffer output of the second bank, high impedance when 2OE is high, with output voltage limited to 0 V to VCC and recommended IOH of -8 mA and IOL of 8 mA. |
| 6 | 1A3 | input | Data input to the first buffer channel, with an input voltage range of 0 V to 5.5 V, TTL-voltage compatible with VIH minimum 2 V and VIL maximum 0.8 V. |
| 7 | 2Y2 | tri_state | 3-state buffer output of the second bank, high impedance when 2OE is high, with output voltage limited to 0 V to VCC and recommended IOH of -8 mA and IOL of 8 mA. |
| 8 | 1A4 | input | Data input to the first buffer channel, with an input voltage range of 0 V to 5.5 V, TTL-voltage compatible with VIH minimum 2 V and VIL maximum 0.8 V. |
| 9 | 2Y1 | tri_state | 3-state buffer output of the second bank, high impedance when 2OE is high, with output voltage limited to 0 V to VCC and recommended IOH of -8 mA and IOL of 8 mA. |
| 10 | GND | power_in | Device ground connection. |
| 11 | 2A1 | input | Data input to the second buffer channel, with an input voltage range of 0 V to 5.5 V, TTL-voltage compatible with VIH minimum 2 V and VIL maximum 0.8 V. |
| 12 | 1Y4 | tri_state | 3-state buffer output of the first bank, high impedance when 1OE is high, with output voltage limited to 0 V to VCC and recommended IOH of -8 mA and IOL of 8 mA. |
| 13 | 2A2 | input | Data input to the second buffer channel, with an input voltage range of 0 V to 5.5 V, TTL-voltage compatible with VIH minimum 2 V and VIL maximum 0.8 V. |
| 14 | 1Y3 | tri_state | 3-state buffer output of the first bank, high impedance when 1OE is high, with output voltage limited to 0 V to VCC and recommended IOH of -8 mA and IOL of 8 mA. |
| 15 | 2A3 | input | Data input to the second buffer channel, with an input voltage range of 0 V to 5.5 V, TTL-voltage compatible with VIH minimum 2 V and VIL maximum 0.8 V. |
| 16 | 1Y2 | tri_state | 3-state buffer output of the first bank, high impedance when 1OE is high, with output voltage limited to 0 V to VCC and recommended IOH of -8 mA and IOL of 8 mA. |
| 17 | 2A4 | input | Data input to the second buffer channel, with an input voltage range of 0 V to 5.5 V, TTL-voltage compatible with VIH minimum 2 V and VIL maximum 0.8 V. |
| 18 | 1Y1 | tri_state | 3-state buffer output of the first bank, high impedance when 1OE is high, with output voltage limited to 0 V to VCC and recommended IOH of -8 mA and IOL of 8 mA. |
| 19 | 2OE | input | Active-low output enable for the second 4-bit buffer; when low the 2Y outputs follow the 2A inputs, and when high the 2Y outputs go to the high-impedance state. |
| 20 | VCC | power_in | Supply voltage, recommended range 4.5 V to 5.5 V; tie OE to VCC through a pullup resistor to keep outputs high-impedance during power up or down. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-20 |
| Category | Logic |
| Pins | 20 |
## CAD (KiCad official)
- Symbol: `SN74AHCT244MPWREP`
- Footprint: `Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm`
- 3D model: TSSOP-20 (KiCad packages3D, STEP)
- 3D model files: `sn74ahct244mpwrep-etched.step` / `sn74ahct244mpwrep-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74ahct244mpwrep.step` / `sn74ahct244mpwrep.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/sn74ahct244-ep) (10 pp, sha256 `ef24c4b9d7fff0f9`, retrieved 2026-10-11, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/sn74ahct244mpwrep-datasheet.pdf)