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SN74AHCT1G86DCKR

Public Made by Adom

by adom

UMW Gates, SC-70-5. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs sn74ahct1g86dckr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
package.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
pads.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
page.json sn74ahct1g86dckr: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC… · Ray
README.md sn74ahct1g86dckr: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray
sn74ahct1g86dckr-etched.fit.json sn74ahct1g86dckr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
sn74ahct1g86dckr-etched.glb sn74ahct1g86dckr: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC… · Ray
sn74ahct1g86dckr-etched.step sn74ahct1g86dckr: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC… · Ray
sn74ahct1g86dckr.glb Publish 0.1.0 · Ray
sn74ahct1g86dckr.kicad_mod Publish 0.1.0 · Ray
sn74ahct1g86dckr.kicad_sym Publish 0.1.0 · Ray
sn74ahct1g86dckr.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect an… · Ray
sn74ahct1g86dckr.step Publish 0.1.0 · Ray

SN74AHCT1G86DCKR

UMW · Gates · SC-70-5

SN74AHCT1G86DCKR from UMW, in a SC-70-5. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A input Logic input A of the 2-input XOR gate. TTL-compatible input (VIH ≥ 2 V, VIL ≤ 0.8 V) over VCC = 4.5-5.5 V. Input current is ±1 µA max; input capacitance is typically 3 pF.
2 B input Logic input B of the 2-input XOR gate. TTL-compatible input (VIH ≥ 2 V, VIL ≤ 0.8 V) over VCC = 4.5-5.5 V. Input current is ±1 µA max; input capacitance is typically 3 pF.
3 GND power_in Ground reference (0 V) for the device. Must be connected to the system ground with a low-impedance return.
4 Y output Push-pull XOR output, Y = A ⊕ B. Sources/sinks up to 8 mA at VCC = 4.5 V with VOH ≥ 3.8 V and VOL ≤ 0.44 V. Typical propagation delay 2.5 ns (CL = 15 pF, VCC = 5 V).
5 VCC power_in Positive supply pin. Recommended operating range 4.5 V to 5.5 V (abs max 7 V). Quiescent supply current ICC ≤ 10 µA. Decouple locally with a 0.1 µF ceramic capacitor to GND.

Key specifications

Parameter Value
Manufacturer UMW
Package SC-70-5
Category Logic
Pins 5

Ordering variants

Same part, different packaging or reel option.

  • SN74AHCT1G86DCKR
  • SN74AHCT1G86DCKRDCKT
  • SN74AHCT1G86DCKRDBVR
  • SN74AHCT1G86DCKRDBVT

CAD (KiCad official)

  • Symbol: SN74AHCT1G86DCKR
  • Footprint: Package_TO_SOT_SMD:SOT-353_SC-70-5
  • 3D model: SC-70-5 (KiCad packages3D, STEP)
  • 3D model files: sn74ahct1g86dckr-etched.step / sn74ahct1g86dckr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74ahct1g86dckr.step / sn74ahct1g86dckr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: UMW datasheet (10 pp, sha256 d14d8246285303c2, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF