SN74AHCT1G02DBVR

{
 "schema": "adom.pads/1",
 "slug": "sn74ahct1g02dbvr",
 "footprint": "SOT-23-5",
 "generated_from": {
  "footprint": "SOT-23-5@sha256:455a3f7c3e5eb5b8",
  "pins": "page.json:component.pins",
  "overrides": null
 },
 "pin1": {
  "pad": "1",
  "at": [
   -1.1375,
   -0.95
  ],
  "corner": "top-left",
  "source": "silk-marker",
  "derived_from": "SOT-23-5@sha256:455a3f7c3e5eb5b8"
 },
 "pad_count": 5,
 "symbol_pins": [
  "1",
  "2",
  "3",
  "4",
  "5"
 ],
 "paste_apertures": 0,
 "issues": [],
 "pads": [
  {
   "pad": "1",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    -1.1375,
    -0.95
   ],
   "rot": 0.0,
   "size": [
    1.325,
    0.6
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "1",
   "name": "A",
   "type": "input",
   "description": "Logic input A of the 2-input NOR gate. TTL-voltage compatible (VIH min 2 V, VIL max 0.8 V). Input clamp current limited to -20 mA per absolute maximum ratings.",
   "is_pin1": true,
   "source": {
    "geometry": "SOT-23-5.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "2",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    -1.1375,
    0.0
   ],
   "rot": 0.0,
   "size": [
    1.325,
    0.6
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "2",
   "name": "B",
   "type": "input",
   "description": "Logic input B of the 2-input NOR gate. TTL-voltage compatible (VIH min 2 V, VIL max 0.8 V). Unused inputs must be tied to VCC or GND.",
   "is_pin1": false,
   "source": {
    "geometry": "SOT-23-5.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "3",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    -1.1375,
    0.95
   ],
   "rot": 0.0,
   "size": [
    1.325,
    0.6
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "3",
   "name": "GND",
   "type": "power_in",
   "description": "Ground reference pin (0 V). Return for VCC supply current and all logic-low output current.",
   "is_pin1": false,
   "source": {
    "geometry": "SOT-23-5.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "4",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    1.1375,
    0.95
   ],
   "rot": 0.0,
   "size": [
    1.325,
    0.6
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "4",
   "name": "Y",
   "type": "output",
   "description": "NOR gate output, Y = NOT(A OR B). Push-pull CMOS output with ±8 mA drive at 5 V. VOH ≥ 3.8 V and VOL ≤ 0.44 V at IO = ±8 mA, VCC = 4.5 V.",
   "is_pin1": false,
   "source": {
    "geometry": "SOT-23-5.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "5",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    1.1375,
    -0.95
   ],
   "rot": 0.0,
   "size": [
    1.325,
    0.6
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "5",
   "name": "VCC",
   "type": "power_in",
   "description": "Positive supply voltage input, 4.5 V to 5.5 V recommended (7 V absolute max). ICC ≤ 10 µA quiescent. Bypass with a 0.1 µF ceramic capacitor placed close to the pin.",
   "is_pin1": false,
   "source": {
    "geometry": "SOT-23-5.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  }
 ]
}