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SN74AHCT174PWR

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Texas Instruments Logic ICs, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN74AHCT174PWR

Texas Instruments · Logic ICs · TSSOP-16

SN74AHCT174PWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CLR input Active-low clear input that resets all six channels when taken low, independent of CLK and D.
2 1Q output Channel 1 Q output.
3 1D input Channel 1 D data input, transferred to 1Q on the rising edge of CLK.
4 2D input Channel 2 D data input, transferred to 2Q on the rising edge of CLK.
5 2Q output Channel 2 Q output.
6 3D input Channel 3 D data input, transferred to 3Q on the rising edge of CLK.
7 3Q output Channel 3 Q output.
8 GND power_in Ground reference for the device.
9 CLK input Common clock for all channels; the flip-flops are triggered on the rising edge.
10 4Q output Channel 4 Q output.
11 4D input Channel 4 D data input, transferred to 4Q on the rising edge of CLK.
12 5Q output Channel 5 Q output.
13 5D input Channel 5 D data input, transferred to 5Q on the rising edge of CLK.
14 6D input Channel 6 D data input, transferred to 6Q on the rising edge of CLK.
15 6Q output Channel 6 Q output.
16 VCC power_in Positive supply pin for the device.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-16
Category Logic ICs
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage range VCC -0.5 7 V 4
Input voltage range VI -0.5 7 V 4
Output voltage range VO -0.5 V Maximum printed as VCC + 0.5 V 4
Input clamp current IIK -20 mA VI < 0 4
Output clamp current IOK -20 20 mA VO < 0 or VO > VCC 4
Continuous output current IO -25 25 mA VO = 0 to VCC 4
Continuous current through VCC or GND -50 50 mA 4
Storage temperature range Tstg -65 150 °C 4
Supply voltage VCC 4.5 5.5 V 4
High-level input voltage VIH 2 V 4
Low-level input voltage VIL 0.8 V 4
Input voltage VI 0 5.5 V 4
Output voltage VO 0 V Maximum printed as VCC 4
High-level output current IOH -8 mA 4
Low-level output current IOL 8 mA 4
Input transition rise or fall time Δt/Δv 20 ns/V 4
Operating free-air temperature TA -40 85 °C 4
High-level output voltage VOH 4.4 4.5 V IOH = -50 μA, VCC = 4.5 V; min over recommended operating free-air temperature range; typ at TA = 25 °C 5
High-level output voltage VOH 3.8 V IOH = -8 mA, VCC = 4.5 V; min over recommended operating free-air temperature range 5
Low-level output voltage VOL 0.1 V IOL = 50 μA, VCC = 4.5 V; max over recommended operating free-air temperature range 5
Low-level output voltage VOL 0.44 V IOL = 8 mA, VCC = 4.5 V; max over recommended operating free-air temperature range 5
Input current II -1 0.1 1 μA VI = 5.5 V or GND, VCC = 0 V to 5.5 V; min/max over recommended operating free-air temperature range; typ at TA = 25 °C 5
Supply current ICC 4 40 μA VI = VCC or GND, IO = 0, VCC = 5.5 V; max over recommended operating free-air temperature range 5
Change in supply current per input ΔICC 1.35 1.5 μA One input at 3.4 V, other inputs at VCC or GND, VCC = 5.5 V; max over recommended operating free-air temperature range 5
Input capacitance Ci 2 10 pF VI = VCC or GND, VCC = 5 V 5
Quiet output, maximum dynamic VOL VOL(P) 0.8 V VCC = 5 V, CL = 50 pF, TA = 25 °C 5
Quiet output, minimum dynamic VOL VOL(V) -0.8 V VCC = 5 V, CL = 50 pF, TA = 25 °C 5
Quiet output, minimum dynamic VOH VOH(V) 4 V VCC = 5 V, CL = 50 pF, TA = 25 °C 6
High-level dynamic input voltage VIH(D) 2 V VCC = 5 V, CL = 50 pF, TA = 25 °C 6
Low-level dynamic input voltage VIL(D) 0.8 V VCC = 5 V, CL = 50 pF, TA = 25 °C 6
Pulse duration, CLR low tw 5 ns Over recommended operating free-air temperature range; VCC = 5 V ± 0.5 V; CLR low 5
Pulse duration, CLK high or low tw 5 ns Over recommended operating free-air temperature range; VCC = 5 V ± 0.5 V; CLK high or low 5
Setup time before CLK↑, data tsu 5 ns Over recommended operating free-air temperature range; VCC = 5 V ± 0.5 V; data 5
Setup time before CLK↑, CLR inactive tsu 3.5 ns Over recommended operating free-air temperature range; VCC = 5 V ± 0.5 V; CLR inactive 5
Hold time, data after CLK↑ th 0 ns Over recommended operating free-air temperature range; VCC = 5 V ± 0.5 V 5
Maximum clock frequency fmax 80 135 MHz CL = 15 pF; min over recommended operating free-air temperature range; typ at TA = 25 °C; VCC = 5 V ± 0.5 V 5
Maximum clock frequency fmax 65 115 MHz CL = 50 pF; min over recommended operating free-air temperature range; typ at TA = 25 °C; VCC = 5 V ± 0.5 V 5
Propagation delay CLR to any Q, high-to-low tPHL 1 10.4 13 ns CL = 15 pF; min/max over recommended operating free-air temperature range; typ at TA = 25 °C; VCC = 5 V ± 0.5 V 5
Propagation delay CLK to any Q, low-to-high tPLH 1 7.8 9 ns CL = 15 pF; min/max over recommended operating free-air temperature range; typ at TA = 25 °C; VCC = 5 V ± 0.5 V 5
Propagation delay CLK to any Q, high-to-low tPHL 1 7.8 9 ns CL = 15 pF; min/max over recommended operating free-air temperature range; typ at TA = 25 °C; VCC = 5 V ± 0.5 V 5
Propagation delay CLR to any Q, high-to-low tPHL 1 11.4 13 ns CL = 50 pF; min/max over recommended operating free-air temperature range; typ at TA = 25 °C; VCC = 5 V ± 0.5 V 5
Propagation delay CLK to any Q, low-to-high tPLH 1 8.8 10 ns CL = 50 pF; min/max over recommended operating free-air temperature range; typ at TA = 25 °C; VCC = 5 V ± 0.5 V 5
Propagation delay CLK to any Q, high-to-low tPHL 1 8.8 10 ns CL = 50 pF; min/max over recommended operating free-air temperature range; typ at TA = 25 °C; VCC = 5 V ± 0.5 V 5
Output skew tsk(o) 1 ns CL = 50 pF; VCC = 5 V ± 0.5 V 5
Junction-to-ambient thermal resistance RθJA 135.9 °C/W PW (TSSOP) package, 16 pins 4

CAD (KiCad official)

  • Symbol: SN74AHCT174PWR
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: sn74ahct174pwr-etched.step / sn74ahct174pwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74ahct174pwr.step / sn74ahct174pwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (28 pp, sha256 544ad23731011800, retrieved 2026-10-18, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF