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SN74AHCT126QPWREP
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Texas Instruments Buffers, Drivers, Receivers, Transceivers, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+50@@ -0,0 +1,50 @@+# SN74AHCT126QPWREP++**Texas Instruments** · Buffers, Drivers, Receivers, Transceivers · TSSOP-14++SN74AHCT126QPWREP from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | 1OE | input | Output enable for gate 1; when low, the 1Y output is disabled (high-impedance), and when high, the gate passes the 1A input to 1Y. |+| 2 | 1A | input | Data input for buffer gate 1, which is TTL-voltage compatible and may be driven from 0 V to 5.5 V. |+| 3 | 1Y | tri_state | 3-state buffer output for gate 1, rated for IOH of -8 mA and IOL of 8 mA. |+| 4 | 2OE | input | Output enable for gate 2; when low, the 2Y output is disabled (high-impedance), and when high, the gate passes the 2A input to 2Y. |+| 5 | 2A | input | Data input for buffer gate 2, which is TTL-voltage compatible and may be driven from 0 V to 5.5 V. |+| 6 | 2Y | tri_state | 3-state buffer output for gate 2, rated for IOH of -8 mA and IOL of 8 mA. |+| 7 | GND | power_in | Ground reference; OE should be tied to GND through a pulldown resistor to hold outputs high-impedance during power up or power down. |+| 8 | 3Y | tri_state | 3-state buffer output for gate 3, rated for IOH of -8 mA and IOL of 8 mA. |+| 9 | 3A | input | Data input for buffer gate 3, which is TTL-voltage compatible and may be driven from 0 V to 5.5 V. |+| 10 | 3OE | input | Output enable for gate 3; when low, the 3Y output is disabled (high-impedance), and when high, the gate passes the 3A input to 3Y. |+| 11 | 4Y | tri_state | 3-state buffer output for gate 4, rated for IOH of -8 mA and IOL of 8 mA. |+| 12 | 4A | input | Data input for buffer gate 4, which is TTL-voltage compatible and may be driven from 0 V to 5.5 V. |+| 13 | 4OE | input | Output enable for gate 4; when low, the 4Y output is disabled (high-impedance), and when high, the gate passes the 4A input to 4Y. |+| 14 | VCC | power_in | Supply voltage, recommended operating range 4.5 V to 5.5 V. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | TSSOP-14 |+| Category | Logic |+| Pins | 14 |++## CAD (KiCad official)++- Symbol: `SN74AHCT126QPWREP`+- Footprint: `Package_SO:TSSOP-14_4.4x5mm_P0.65mm`+- 3D model: TSSOP-14 (KiCad packages3D, STEP)+- 3D model files: `sn74ahct126qpwrep-etched.step` / `sn74ahct126qpwrep-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74ahct126qpwrep.step` / `sn74ahct126qpwrep.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/sn74ahct126-ep) (15 pp, sha256 `826a4879f252d48e`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/sn74ahct126qpwrep-datasheet.pdf)
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when low, the 1Y output is disabled (high-impedance), and when high, the gate passes the 1A input to 1Y."+ },+ {+ "number": "2",+ "name": "1A",+ "type": "input",+ "description": "Data input for buffer gate 1, which is TTL-voltage compatible and may be driven from 0 V to 5.5 V."+ },+ {+ "number": "3",+ "name": "1Y",+ "type": "tri_state",+ "description": "3-state buffer output for gate 1, rated for IOH of -8 mA and IOL of 8 mA."+ },+ {+ "number": "4",+ "name": "2OE",+ "type": "input",+ "description": "Output enable for gate 2; when low, the 2Y output is disabled (high-impedance), and when high, the gate passes the 2A input to 2Y."+ },+ {+ "number": "5",+ "name": "2A",+ "type": "input",+ "description": "Data input for buffer gate 2, which is TTL-voltage compatible and may be driven from 0 V to 5.5 V."+ },+ {+ "number": "6",+ "name": "2Y",+ "type": "tri_state",+ "description": "3-state buffer output for gate 2, rated for IOH of -8 mA and IOL of 8 mA."+ },+ {+ "number": "7",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference; OE should be tied to GND through a pulldown resistor to hold outputs high-impedance during power up or power down."+ },+ {+ "number": "8",+ "name": "3Y",+ "type": "tri_state",+ "description": "3-state buffer output for gate 3, rated for IOH of -8 mA and IOL of 8 mA."+ },+ {+ "number": "9",+ "name": "3A",+ "type": "input",+ "description": "Data input for buffer gate 3, which is TTL-voltage compatible and may be driven from 0 V to 5.5 V."+ },+ {+ "number": "10",+ "name": "3OE",+ "type": "input",+ "description": "Output enable for gate 3; when low, the 3Y output is disabled (high-impedance), and when high, the gate passes the 3A input to 3Y."+ },+ {+ "number": "11",+ "name": "4Y",+ "type": "tri_state",+ "description": "3-state buffer output for gate 4, rated for IOH of -8 mA and IOL of 8 mA."+ },+ {+ "number": "12",+ "name": "4A",+ "type": "input",+ "description": "Data input for buffer gate 4, which is TTL-voltage compatible and may be driven from 0 V to 5.5 V."+ },+ {+ "number": "13",+ "name": "4OE",+ "type": "input",+ "description": "Output enable for gate 4; when low, the 4Y output is disabled (high-impedance), and when high, the gate passes the 4A input to 4Y."+ },+ {+ "number": "14",+ "name": "VCC",+ "type": "power_in",+ "description": "Supply voltage, recommended operating range 4.5 V to 5.5 V."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: GND (pin 7) and VCC (pin 14) are taken from the TSSOP top-view pin listing, whose text extraction is; The datasheet's ordering table lists SN74AHCT126QPWREP as a TSSOP-PW part, so the TSSOP-14 pinout ap"+ ],+ "pages_sent": 15,+ "cost_usd": 0.0698,+ "at": "2026-10-08T16:33:40"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/sn74ahct126-ep",+ "pages": 15,+ "sha256": "826a4879f252d48e",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 14,+ "described": 14,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "sn74ahct126qpwrep.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.4,+ 5,+ 1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "3ee5786aae56190997aa793ba3cfc003fd616782770e29719b4562f012982245",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "sn74ahct126qpwrep-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.4,+ 5,+ 1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "fd96606fb6dcdfff6611235ed316c1c6306eb6d278fd6f4fbd3c4c515cf99fb8",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}