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SN74AHCT126QPWREP
Public Made by Adomby adom
Texas Instruments Buffers, Drivers, Receivers, Transceivers, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSN74AHCT126QPWREP
Texas Instruments · Buffers, Drivers, Receivers, Transceivers · TSSOP-14
SN74AHCT126QPWREP from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1OE | input | Output enable for gate 1; when low, the 1Y output is disabled (high-impedance), and when high, the gate passes the 1A input to 1Y. |
| 2 | 1A | input | Data input for buffer gate 1, which is TTL-voltage compatible and may be driven from 0 V to 5.5 V. |
| 3 | 1Y | tri_state | 3-state buffer output for gate 1, rated for IOH of -8 mA and IOL of 8 mA. |
| 4 | 2OE | input | Output enable for gate 2; when low, the 2Y output is disabled (high-impedance), and when high, the gate passes the 2A input to 2Y. |
| 5 | 2A | input | Data input for buffer gate 2, which is TTL-voltage compatible and may be driven from 0 V to 5.5 V. |
| 6 | 2Y | tri_state | 3-state buffer output for gate 2, rated for IOH of -8 mA and IOL of 8 mA. |
| 7 | GND | power_in | Ground reference; OE should be tied to GND through a pulldown resistor to hold outputs high-impedance during power up or power down. |
| 8 | 3Y | tri_state | 3-state buffer output for gate 3, rated for IOH of -8 mA and IOL of 8 mA. |
| 9 | 3A | input | Data input for buffer gate 3, which is TTL-voltage compatible and may be driven from 0 V to 5.5 V. |
| 10 | 3OE | input | Output enable for gate 3; when low, the 3Y output is disabled (high-impedance), and when high, the gate passes the 3A input to 3Y. |
| 11 | 4Y | tri_state | 3-state buffer output for gate 4, rated for IOH of -8 mA and IOL of 8 mA. |
| 12 | 4A | input | Data input for buffer gate 4, which is TTL-voltage compatible and may be driven from 0 V to 5.5 V. |
| 13 | 4OE | input | Output enable for gate 4; when low, the 4Y output is disabled (high-impedance), and when high, the gate passes the 4A input to 4Y. |
| 14 | VCC | power_in | Supply voltage, recommended operating range 4.5 V to 5.5 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-14 |
| Category | Logic |
| Pins | 14 |
CAD (KiCad official)
- Symbol:
SN74AHCT126QPWREP - Footprint:
Package_SO:TSSOP-14_4.4x5mm_P0.65mm - 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files:
sn74ahct126qpwrep-etched.step/sn74ahct126qpwrep-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74ahct126qpwrep.step/sn74ahct126qpwrep.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (15 pp, sha256
826a4879f252d48e, retrieved 2026-10-08, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).