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SN74AHCT125QPWRQ1

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Texas Instruments Buffers, Drivers, Receivers, Transceivers, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN74AHCT125QPWRQ1

Texas Instruments · Buffers, Drivers, Receivers, Transceivers · TSSOP-14

SN74AHCT125QPWRQ1 from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1OE input Output enable for gate 1; when high the 1Y output is disabled to high impedance, and when low the gate passes data from 1A to 1Y.
2 1A input Data input of buffer 1, TTL-voltage compatible, passed to output 1Y when 1OE is low.
3 1Y tri_state 3-state output of buffer 1, high impedance whenever 1OE is high.
4 2OE input Output enable for gate 2; when high the 2Y output is disabled to high impedance, and when low the gate passes data from 2A to 2Y.
5 2A input Data input of buffer 2, TTL-voltage compatible, passed to output 2Y when 2OE is low.
6 2Y tri_state 3-state output of buffer 2, high impedance whenever 2OE is high.
7 GND power_in Ground reference for the device; unused inputs must be held at VCC or GND for proper operation.
8 3Y tri_state 3-state output of buffer 3, high impedance whenever 3OE is high.
9 3A input Data input of buffer 3, TTL-voltage compatible, passed to output 3Y when 3OE is low.
10 3OE input Output enable for gate 3; when high the 3Y output is disabled to high impedance, and when low the gate passes data from 3A to 3Y.
11 4Y tri_state 3-state output of buffer 4, high impedance whenever 4OE is high.
12 4A input Data input of buffer 4, TTL-voltage compatible, passed to output 4Y when 4OE is low.
13 4OE input Output enable for gate 4; when high the 4Y output is disabled to high impedance, and when low the gate passes data from 4A to 4Y.
14 VCC power_in Supply voltage, recommended range 4.5 V to 5.5 V; OE should be tied to VCC through a pullup resistor to hold the outputs in high impedance during power up or down.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 4.5 5.5 V 3
High-level input voltage VIH 2 V 3
Low-level input voltage VIL 0.8 V 3
Input voltage VI 0 5.5 V 3
Output voltage VO 0 V max VCC 3
High-level output current IOH -8 mA 3
Low-level output current IOL 8 mA 3
Input transition rise or fall rate Δt/Δv 20 ns/V 3
Operating free-air temperature TA -40 125 °C 3
Supply voltage range VCC -0.5 7 V 2
Input voltage range VI -0.5 7 V see Note 1 2
Output voltage range VO -0.5 V max VCC + 0.5 V, see Note 1 2
Input clamp current IIK -20 mA VI < 0 2
Output clamp current IOK -20 20 mA VO < 0 or VO > VCC 2
Continuous output current IO -25 25 mA VO = 0 to VCC 2
Continuous current through VCC or GND -50 50 mA 2
Storage temperature range Tstg -65 150 °C 2
Package thermal impedance PW package θJA 113 °C/W PW package, JESD 51-7 2
High-level output voltage VOH 4.4 V IOH = −50 µA, VCC = 4.5 V 3
High-level output voltage VOH 3.8 V IOH = −8 mA, VCC = 4.5 V 3
Low-level output voltage VOL 0.1 V IOL = 50 µA, VCC = 4.5 V 3
Low-level output voltage VOL 0.44 V IOL = 8 mA, VCC = 4.5 V 3
Input leakage current II -1 1 µA VI = 5.5 V or GND, 0 V to 5.5 V 3
Off-state (high-impedance) output current IOZ -2.5 2.5 µA VO = VCC or GND, 5.5 V 3
Quiescent supply current ICC 20 µA VI = VCC or GND, IO = 0, VCC 5.5 V 3
Increase in supply current per input at TTL level ΔICC 1.35 1.5 mA One input at 3.4 V, other inputs at VCC or GND, VCC 5.5 V 3
Input capacitance Ci 4 10 pF VI = VCC or GND, 5 V 3
Output capacitance Co 15 pF VO = VCC or GND, 5 V 3
Propagation delay A to Y tPLH 1 6.5 ns CL = 15 pF, VCC = 5 V ± 0.5 V 4
Enable time OE to Y tPZH 1 6 ns CL = 15 pF, VCC = 5 V ± 0.5 V 4
Disable time OE to Y tPHZ 1 8 ns CL = 15 pF, VCC = 5 V ± 0.5 V 4
Propagation delay A to Y tPLH 1 8.5 ns CL = 50 pF, VCC = 5 V ± 0.5 V 4
Enable time OE to Y tPZH 1 8 ns CL = 50 pF, VCC = 5 V ± 0.5 V 4
Disable time OE to Y tPHZ 1 10 ns CL = 50 pF, VCC = 5 V ± 0.5 V 4
Output skew tsk(o) 1 ns CL = 50 pF 4
Quiet output maximum dynamic VOL VOL(P) 0.8 V VCC = 5 V, CL = 50 pF, TA = 25°C 4
Quiet output minimum dynamic VOL VOL(V) -0.8 V VCC = 5 V, CL = 50 pF, TA = 25°C 4
Quiet output minimum dynamic VOH VOH(V) 4.4 V VCC = 5 V, CL = 50 pF, TA = 25°C 4
High-level dynamic input voltage VIH(D) 2 V VCC = 5 V, CL = 50 pF, TA = 25°C 4
Low-level dynamic input voltage VIL(D) 0.8 V VCC = 5 V, CL = 50 pF, TA = 25°C 4

CAD (KiCad official)

  • Symbol: SN74AHCT125QPWRQ1
  • Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
  • 3D model: TSSOP-14 (KiCad packages3D, STEP)
  • 3D model files: sn74ahct125qpwrq1-etched.step / sn74ahct125qpwrq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74ahct125qpwrq1.step / sn74ahct125qpwrq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (14 pp, sha256 8b326c21fdd36d5a, retrieved 2026-10-27, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus off (skipped (clean text read)), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF