component
SN74AHCT125DR
Public Made by Adomby adom
Texas Instruments Buffer/Driver/Transceiver, SOIC-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSN74AHCT125DR
Texas Instruments · Buffer/Driver/Transceiver · SOIC-14
SN74AHCT125DR from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1OE | input | Active-low output enable for gate 1. When low, 1Y follows 1A; when high, 1Y is in high-impedance state. TTL-compatible input, VIH >= 2 V, VIL <= 0.8 V. |
| 2 | 1A | input | Gate 1 data input. TTL-compatible logic input to buffer 1. |
| 3 | 1Y | tri_state | Gate 1 3-state output. Drives the buffered value of 1A when 1OE is low; high-Z when 1OE is high. IOH/IOL = +/-8 mA at VCC = 4.5-5.5 V. |
| 4 | 2OE | input | Active-low output enable for gate 2. When low, 2Y follows 2A; when high, 2Y is in high-impedance state. |
| 5 | 2A | input | Gate 2 data input. TTL-compatible logic input to buffer 2. |
| 6 | 2Y | tri_state | Gate 2 3-state output. Drives the buffered value of 2A when 2OE is low; high-Z when 2OE is high. |
| 7 | GND | power_in | Ground reference (0 V). Ties to system ground. |
| 8 | 3Y | tri_state | Gate 3 3-state output. Drives the buffered value of 3A when 3OE is low; high-Z when 3OE is high. |
| 9 | 3A | input | Gate 3 data input. TTL-compatible logic input to buffer 3. |
| 10 | 3OE | input | Active-low output enable for gate 3. When low, 3Y follows 3A; when high, 3Y is in high-impedance state. |
| 11 | 4Y | tri_state | Gate 4 3-state output. Drives the buffered value of 4A when 4OE is low; high-Z when 4OE is high. |
| 12 | 4A | input | Gate 4 data input. TTL-compatible logic input to buffer 4. |
| 13 | 4OE | input | Active-low output enable for gate 4. When low, 4Y follows 4A; when high, 4Y is in high-impedance state. |
| 14 | VCC | power_in | Positive supply voltage. Recommended operating range 4.5 V to 5.5 V (absolute max 7 V). Bypass with a 0.1 uF ceramic capacitor to GND close to the pin. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-14 |
| Category | Logic |
| Pins | 14 |
Ordering variants
Same part, different packaging or reel option.
SN74AHCT125DRDSN74AHCT125DRSN74AHCT125DRDBSN74AHCT125DRDBRSN74AHCT125DRDGVSN74AHCT125DRDGVRSN74AHCT125DRNSN74AHCT125DRNSSN74AHCT125DRNSRSN74AHCT125DRPWSN74AHCT125DRPWRSN74AHCT125DRRGYSN74AHCT125DRRGYRSN74AHCT125DRBQASN74AHCT125DRBQARSN74AHCT125DRJSN74AHCT125DRWSN74AHCT125DRFK
CAD (KiCad official)
- Symbol:
SN74AHCT125DR - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files:
sn74ahct125dr-etched.step/sn74ahct125dr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74ahct125dr.step/sn74ahct125dr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (44 pp, sha256
0f6a373471f0b946, retrieved 2026-08-17, tier: manufacturer) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).